Systems and Methods for Mura Calibration Preparation

• US 20130328759A1
• Filed: 08/31/2012
• Published: 12/12/2013
• Est. Priority Date: 06/08/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Al-Dahle, Ahmad, Stronks, David A., Bae, Hopil
• Granted Patent: US 9,519,164 B2
• Time in Patent Office: Days
• US Class Current: 345/89
• CPC Class Codes: G02F 1/1309 Repairing; Testing
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: G09G 2320/0693 Calibration of display systems

Abstract

Systems and methods for calibrating an electronic display to reduce or eliminate artifacts are provided. One method for reducing or eliminating artifacts may involve baking the operational—but not yet fully calibrated—electronic display to reduce stray charge on the electronic display. After baking the display, the electronic display may be calibrated to reduce or eliminate flicker and/or mura artifacts

Claims

1. A method for manufacturing an electronic display comprising:

baking the electronic display to reduce stray charge on the electronic display, wherein the electronic display is configured to be sufficiently operational so as to be capable of being calibrated; and

calibrating the electronic display to reduce artifacts after baking the display.

2. The method of claim 1, wherein calibrating the electronic display comprises tuning the electronic display to reduce or eliminate a mura artifact.

3. The method of claim 1, wherein calibrating the electronic display comprises tuning the electronic display to reduce or eliminate flicker.

4. The method of claim 3, wherein the electronic display is tuned to reduce or eliminate flicker while pixels of the electronic display are programmed to display a gray level configured to produce a stronger contrast of a mura artifact than most other gray levels.

5. The method of claim 3, wherein the electronic display is tuned to reduce or eliminate flicker while pixels of the electronic display are programmed to display a gray level of between G40 to G80 on a scale from G0 to G255.

6. The method of claim 3, wherein the electronic display is tuned to reduce or eliminate flicker while pixels of the electronic display are programmed to display a gray level configured to produce a stronger contrast of a mura artifact than all other gray levels.

7. The method of claim 3, wherein the electronic display is tuned to reduce or eliminate flicker while pixels of the electronic display are programmed to display a gray level of G63 on a scale from G0 to G255.

8. A method for manufacturing an electronic display, comprising:

providing a liquid crystal display, wherein the liquid crystal display comprises a plurality of common voltage layers (VCOMs) configured to cause a mura artifact to appear on the liquid crystal display when the liquid crystal display is operated;

baking the liquid crystal display to reduce stray charge; and

calibrating an operating parameter of the liquid crystal display to reduce or eliminate the mura after the stray charge has been reduced due to baking.

9. The method of claim 8, wherein the method is performed before the liquid crystal display is installed into a host electronic device.

10. The method of claim 8, wherein the method is performed while the liquid crystal display is installed in a host electronic device.

11. The method of claim 8, wherein the liquid crystal display is baked at a temperature of between 40 and 60 degrees Celsius.

12. The method of claim 8, wherein the liquid crystal display is baked for a period of time configured to cause substantially all stray charge on the liquid crystal display due to prior manufacturing steps to become dissipated.

13. The method of claim 8, wherein the liquid crystal display is baked at a humidity higher than typically employed during liquid crystal display manufacturing.

14. The method of claim 8, wherein the liquid crystal display is baked at a humidity of between 40 and 60 percent.

15. The method of claim 8, wherein the liquid crystal display is baked a humidity higher than prior manufacturing steps to prevent electrostatic discharge from damaging the liquid crystal display.

16. A method for manufacturing an electronic device, comprising:

installing an electronic display into the electronic device, wherein stray charge accumulates on components of the electronic display during installation;

baking the electronic device to cause the stray charge to dissipate from the components of the electronic display; and

calibrating the electronic display while the stray charge is dissipated.

17. The method of claim 16, wherein calibrating the electronic display comprises:

tuning the electronic display to reduce or eliminate flicker while the electronic display is programmed to display a gray level that produces a stronger contrast of a mura artifact than most other gray levels; and

tuning the electronic display to reduce or eliminate a mura artifact.

18. The method of claim 16, wherein the electronic device comprises a handheld device, a portable phone, a notebook computer, a tablet computer, or a desktop computer, or any combination thereof.

19. A method for calibrating an electronic display, comprising:

programming pixels of the electronic display to a gray level configured to produce a stronger contrast in the mura than most other gray levels;

tuning the electronic display to reduce flicker while the pixels are programmed to the gray level; and

after the electronic display has been tuned to reduce flicker, tuning the electronic display to reduce or eliminate a mura artifact.

20. The method of claim 19, wherein the gray level comprises a gray level configured to produce a stronger contrast in the mura than all other gray levels.

21. The method of claim 19, wherein the gray level comprises a gray level of between about G40 to G80 on a scale from G0 to G255.

22. The method of claim 19, wherein the gray level comprises a gray level of G63 on a scale from G0 to G255.

23. The method of claim 19, wherein the electronic display comprises a liquid crystal display, wherein the liquid crystal display comprises a plurality of common voltage layers (VCOMs) and wherein the mura artifact is due to the VCOMs.

24. The method of claim 23, wherein tuning the electronic display to reduce or eliminate the mura artifact comprises adjusting a gate clock overlap, a gate clock fall time, a source output parking voltage, or a differential resistance of the VCOMs, or any combination thereof.