COLUMN SPACER DESIGN FOR A DISPLAY INCORPORATING A THIRD METAL LAYER

• US 20130329150A1
• Filed: 09/06/2012
• Published: 12/12/2013
• Est. Priority Date: 06/06/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Cheng Chen, John Z. Zhong, Kyung-Wook Kim, Shih Chang Chang, Young-Bae Park
• Inventors: Chang, Shih Chang, Chen, Cheng, Park, Young-Bae, Zhong, John Z., KIM, Kyung-Wook
• Granted Patent: US 9,395,583 B2
• Time in Patent Office: Days
• US Class Current: 349/42
• CPC Class Codes: G02F 1/133302 Rigid substrates, e.g. inorganic substrates
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 1/133514 Colour filters
• CPC Class Codes: G02F 1/13394 spacers regularly patterned on the cell subtrate, e.g. walls, pillars G02F1/133377 takes precedence
• CPC Class Codes: G02F 1/13396 Spacers having different sizes
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/12 electrode
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Abstract

A display that contains a column spacer arrangement which takes advantage of a protrusion on a TFT substrate is provided. One set of column spacers is disposed on top of the protrusion, while a second set of column spacers of substantially the same height as the first set of column spacers are disposed throughout the display. In this way, the display is adequately protected against deformation from external forces while at the same maintaining enough room to allow for a liquid crystal to spread out during the manufacturing process.

Claims

1. A display pixel stackup, comprising:

a top cover;

a transistor substrate;

a fluid layer disposed between the top cover and the transistor substrate; and

a plurality of column spacer sets wherein at least a first set of column spacers is disposed above a protrusion of the transistor substrate.

2. The display of claim 1, wherein the transistor substrate is a TFT substrate, and the protrusion of the transistor substrate is created by a pixel TFT of the TFT substrate.

3. The display of claim 2, wherein the first set of column spacers are disposed on top of a plurality of pixel TFTs.

4. The display of claim 1, wherein the protrusion of the transistor substrate is created by a metal layer and an active layer of the transistor substrate.

5. The display of claim 4, wherein the metal layer is deposited on a plurality of common electrodes of the display.

6. The display of claim 5, wherein the plurality of common electrodes are disposed on the TFT substrate in a common on top arrangement.

7. The display of claim 5, wherein the plurality of common electrodes are disposed on the transistor substrate in a common on bottom arrangement.

8. The display of claim 1, wherein the first set of column spacers is disposed above the protrusion of the transistor substrate such that the first set of column spacers directly touches the protrusion on the transistor substrate.

9. The display of claim 7, wherein the first set of column spacers directly touches a metal layer.

10. The display of claim 7, wherein the first set of column spacers directly touches a dielectric material disposed on top of a metal layer.

11. The display of claim 1 wherein a height of the first set of column spacers is substantially equal to a height of a second set of column spacers within the plurality of column spacer sets.

12. A method of arranging a plurality of column spacer sets on a display pixel stackup, the method comprising:

disposing a first set of column spacers of the plurality of column spacer sets on a protrusion of a transistor substrate of the display pixel stackup; and

disposing a second set of column spacers of the plurality of column spacer sets such that a gap is created between the second set of column spacers and the transistor substrate.

13. The method of claim 12, wherein the transistor substrate is a TFT substrate, and the protrusion of the transistor substrate is created by a pixel TFT of the TFT substrate.

14. The method of claim 12, wherein the protrusion of the transistor substrate is created by a metal layer of the transistor substrate.

15. The method of claim 14, wherein the metal layer is deposited on a plurality of common electrodes of the display.

16. The method of claim 15, wherein the plurality of common electrodes are disposed on the transistor substrate in a common on top arrangement.

17. The method of claim 15, wherein the plurality of common electrodes are disposed on the transistor substrate in a common on bottom arrangement.

18. The method of claim 12, wherein the first set of column spacers is disposed above the protrusion of the transistor substrate such that the first set of column spacers directly touches the protrusion on the transistor substrate.

19. The method of claim 18, wherein the first set of column spacers directly touches a pixel TFT.

20. The method of claim 18, wherein the first set of column spacers directly touches a metal layer.

21. The method of claim 18, wherein the first set of column spacers directly touches a dielectric material disposed on top of a metal layer.

22. The method of claim 12 wherein a height of the first set of column spacers is substantially equal to a height of the second set of column spacers within the plurality of column spacer sets.