METHOD AND SYSTEM FOR ACCELERATING CRYPTOGRAPHIC PROCESSING

• US 20130332744A1
• Filed: 06/05/2013
• Published: 12/12/2013
• Est. Priority Date: 06/08/2012
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Zhuang, Gongyuan
• Granted Patent: US 9,342,712 B2
• Time in Patent Office: Days
• US Class Current: 713/189
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H04L 2209/125 Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
• CPC Class Codes: H04L 9/0631 Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
• CPC Class Codes: H04L 9/0637 Modes of operation, e.g. cipher block chaining [CBC], electronic codebook [ECB] or Galois/counter mode [GCM]
• CPC Class Codes: H04L 9/0643 Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
• CPC Class Codes: H04L 9/3066 involving algebraic varieties, e.g. elliptic or hyper-elliptic curves

Abstract

A method, an apparatus, and a non-transitory computer readable medium for accelerating cryptographic processing are presented. A cryptographic algorithm is parallelized, which includes breaking the cryptographic algorithm into components, parallelizing an entire component if the component is fully parallelizable, parallelizing part of a component if the component is partially parallelizable, and sequentially executing a component if the component is not parallelizable. Processing of the parallelizable component or the partially parallelizable component is distributed to one or more parallelized devices. The parallelized devices include at least one of: a graphics processing unit or a cryptographic processing device, which may include an integrated cryptographic processor or a cryptographic co-processor.

Claims

1. A method for accelerating cryptographic processing, comprising:

parallelizing a cryptographic algorithm, including;

breaking the cryptographic algorithm into components;

parallelizing an entire component if the component is fully parallelizable;

parallelizing part of a component if the component is partially parallelizable; and

sequentially executing a component if the component is not parallelizable; and

distributing processing of the parallelizable component or the partially parallelizable component to one or more parallelized devices.

2. The method according to claim 1, wherein the parallelized devices include at least one of:

a graphics processing unit or a cryptographic processing device.

3. The method according to claim 2, wherein the cryptographic processing device includes an integrated cryptographic processor or a cryptographic co-processor.

4. The method according to claim 2, wherein the cryptographic processing device includes one or more cryptographic engines, each cryptographic engine being specific to a particular cryptographic algorithm.

5. The method according to claim 1, wherein the sequentially executed component is executed on a central processing unit core.

6. A system for accelerating cryptographic processing, comprising:

one or more parallelized devices; and

a central processing unit core, configured to;

parallelize a cryptographic algorithm, including;

break the cryptographic algorithm into components;

parallelize an entire component if the component is fully parallelizable;

parallelize part of a component if the component is partially parallelizable; and

sequentially execute a component if the component is not parallelizable; and

distribute processing of the parallelizable component or the partially parallelizable component to the one or more parallelized devices.

7. The system according to claim 6, wherein the parallelized devices include at least one of:

a graphics processing unit or a cryptographic processing device.

8. The system according to claim 7, wherein the cryptographic processing device includes an integrated cryptographic processor or a cryptographic co-processor.

9. The system according to claim 7, wherein the cryptographic processing device includes one or more cryptographic engines, each cryptographic engine being specific to a particular cryptographic algorithm.

10. The system according to claim 6, wherein the central processing unit core is further configured to executed the sequentially executed component.

11. The system according to claim 6, wherein the central processing unit and the one or more parallelized devices are located on a single die.

12. A non-transitory computer-readable storage medium storing a set of instructions for execution by a general purpose computer to accelerate cryptographic processing, the set of instructions comprising:

a first parallelizing code segment for parallelizing a cryptographic algorithm, including;

a breaking code segment for breaking the cryptographic algorithm into components;

a second parallelizing code segment for parallelizing an entire component if the component is fully parallelizable;

a third parallelizing code segment for parallelizing part of a component if the component is partially parallelizable; and

a sequentially executing code segment for sequentially executing a component if the component is not parallelizable; and

a distributing code segment for distributing processing of the parallelizable component or the partially parallelizable component to one or more parallelized devices.

13. The non-transitory computer-readable storage medium according to claim 12, wherein the instructions are hardware description language (HDL) instructions used for the manufacture of a device.