METHOD, CONTROLLER, AND MEMORY DEVICE FOR CORRECTING DATA BIT(S) OF AT LEAST ONE CELL OF FLASH MEMORY

• US 20130332801A1
• Filed: 06/07/2013
• Published: 12/12/2013
• Est. Priority Date: 06/08/2012
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated Taiwan (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated Taiwan (Silicon Motion)
• Inventors: Yang, Tsung-Chieh, Weng, Chen-Yu
• Granted Patent: US 9,110,824 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

A method for correcting data bit of at least a cell of a flash memory includes: determining a contributing factor of level distribution corresponding to an electric level of a first cell to generate a first determination result; and, correcting/modifying the data bit corresponding to the electric potential of the first cell according to the first determination result.

Claims

1. A method for modifying a data bit of at least a cell of a flash memory, comprising:

(a) determining a contributing factor of level distribution corresponding to an electric level of a first cell to generate a first determination result; and

(b) modifying the data bit corresponding to the electric level of the first cell according to the first determination result.

2. The method of claim 1, wherein the step of generating the first determination result comprises:

determining the contributing factor of level distribution corresponding to the electric level of the first cell according to a data bit of a first adjacent cell.

3. The method of claim 2, wherein the first cell is with four storage states, and the step of determining the contributing factor of level distribution corresponding to the electric level of the first cell comprises:

determining that the contributing factor is a first kind of contributing factor when the data bit of the first adjacent cell indicates an erase state ‘

0’

or a data state ‘

2’

; and

determining that the contributing factor is a second kind of contributing factor when the data bit of the first adjacent cell indicates a data state ‘

1’

or a data state ‘

3’

;

wherein the second kind of contributing factor indicates more level shift impact than that indicated by the first kind of contributing factor.

4. The method of claim 2, wherein the first cell and the first adjacent cell are located at different word lines, and the first adjacent cell is located below the first cell.

5. The method of claim 2, wherein the first cell and the first adjacent cell are located at different word lines, and the first adjacent cell is located above the first cell.

6. The method of claim 1, further comprising:

determining a contributing factor of level distribution corresponding to an electric level of a second cell to generate a second determination result; and

modifying the data bit corresponding to the electric level of the second cell according to the second determination result;

wherein an original data bit of the first cell is equal to a modified data bit of the second cell, a modified data bit of the first cell is equal to an original data bit of the second cell, and a bit flipping operation is formed by respective operations for modifying the data bits of the first and second cells.

7. The method of claim 1, further comprising:

performing an error correction code operation to determine whether error bit(s) of codeword data can be corrected or not; and

performing step (a) to step (b) of claim 1 when the error bit(s) of codeword data cannot be effectively corrected.

8. A controller for modifying a data bit of at least a cell of a flash memory, comprising:

an accessing unit, for reading a data bit corresponding to an electric level of a first cell; and

an error correction code unit, coupled to the accessing unit, for determining a contributing factor of level distribution corresponding to the electric level of the first cell to generate a first determination result, and modifying the data bit corresponding to the electric level of the first cell according to the first determination result.

9. The controller of claim 8, wherein the error correction code unit determines the contributing factor of level distribution corresponding to the electric level of the first cell according to a data bit of a first adjacent cell.

10. The controller of claim 9, wherein the first cell is with four storage states;

the error correction code unit determines that the contributing factor is a first kind of contributing factor when the data bit of the first adjacent cell indicates an erase state ‘

0’

or a data state ‘

2’

;

the error correction code unit determines that the contributing factor is a second kind of contributing factor when the data bit of the first adjacent cell indicates a data state ‘

1’

or a data state ‘

3’

; and

, the second kind of contributing factor indicates more level shift impact than that indicated by the first kind of contributing factor.

11. The controller of claim 9, wherein the first cell and the first adjacent cell are located at different word lines, and the first adjacent cell is located below the first cell.

12. The controller of claim 9, wherein the first cell and the first adjacent cell are located at different word lines, and the first adjacent cell is located above the first cell.

13. The controller of claim 8, wherein the error correction code unit determines a contributing factor of level distribution corresponding to an electric level of a second cell to generate a second determination result, and modifies the data bit corresponding to the electric level of the second cell according to the second determination result;

an original data bit of the first cell is equal to a modified data bit of the second cell, a modified data bit of the first cell is equal to an original data bit of the second cell, and a bit flipping operation is formed by respective operations for modifying the data bits of the first and second cells.

14. The controller of claim 8, wherein the error correction code unit performs an error correction code operation to determine whether error bit(s) of codeword data can be corrected or not;

and, when the error bit(s) of codeword data cannot be effectively corrected, the error correction code unit determines a contributing factor of level distribution corresponding to the electric level of the first cell to generate a first determination result, and modifies the data bit corresponding to the electric level of the first cell according to the first determination result.

15. A memory device, comprising:

a flash memory having a cell with an electric level corresponding to a data bit; and

a memory controller, coupled to the flash memory, for determining a contributing factor of level distribution corresponding to the electric level of the cell to generate a determination result, and modifying the data bit corresponding to the electric level of the cell according to the determination result.