HIGH ENERGY, REAL TIME CAPABLE, DIRECT RADIATION CONVERSION X-RAY IMAGING SYSTEM FOR CD-TE AND CD-ZN-TE BASED CAMERAS

• US 20130334433A1
• Filed: 07/05/2013
• Published: 12/19/2013
• Est. Priority Date: 07/06/2004
• Status: Abandoned Application

• Current Assignee: Oy Ajat Limited
• Original Assignee: Oy Ajat Limited
• Inventors: SPARTIOTIS, Konstantinos, PANTSAR, Tuomas
• Application Number:
  US13/935,663
• Publication Number:
  US 20130334433A1
• Time in Patent Office: Days
• US Class Current: 250/370.09
• CPC Class Codes: G01T 1/24 with semiconductor detectors
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 31/0296 including, apart from doping material or other impurities, only AIIBVI compounds, e.g. CdS, ZnS, HgCdTe
• CPC Class Codes: H04N 25/671 for non-uniformity detection or correction
• CPC Class Codes: H04N 25/673 by using reference sources
• CPC Class Codes: H04N 25/68 applied to defects
• CPC Class Codes: H04N 5/325 Image enhancement, e.g. by subtraction techniques using polyenergetic X-rays

Abstract

A calibrated real-time, high energy X-ray imaging system is disclosed which incorporates a direct radiation conversion, X-ray imaging camera and a high speed image processing module. The high energy imaging camera utilizes a Cd—Te or a Cd—Zn—Te direct conversion detector substrate. The image processor includes a software driven calibration module that uses an algorithm to analyze time dependent raw digital pixel data to provide a time related series of correction factors for each pixel in an image frame. Additionally, the image processor includes a high speed image frame processing module capable of generating image frames at frame readout rates of greater than ten frames per second to over 100 frames per second. The image processor can provide normalized image frames in real-time or can accumulate static frame data for substantially very long periods of time without the typical concomitant degradation of the signal-to-noise ratio.

Claims

1. An x-ray imaging system, comprising:

an x-ray imaging device with an output providing an array of pixels values for producing multiple different individual image frames (44),

each said pixel value generated responsive to absorption of impinging high energy x-ray gamma ray radiation, converted by an analog to digital converter (96) (ADC) providing, at the output of the imaging device, the array of pixel values, each pixel value with a first bit depth (N),

each individual frame of said multiple individual frames comprising the array (45) of the pixel values with the first bit depth (N); and

an image processor connected to receive the array of pixel values from the output of the imaging device, the image processor including a processor (24) calculating final image pixel values (47) of a second bit depth (M) from the pixel values of the first bit depth (N) of the different individual frames, the image processor outputting frames of the final image pixel values (47) of an x-ray image to be displayed on a display,

wherein the second bit depth (M) of the final image pixel values (47) to be displayed is greater than the first bit depth of the pixel values from the individual frames (M>

N) to provide relatively increased resolution of the image data displayed the x-ray image displayed on the display relative to the resolution output from the x-ray imaging device.

2. The system of claim 1, wherein,

the imaging device is a high energy x-ray imaging camera (37), the camera providing an array of pixels values at said output of the analog to digital converter,

the camera having a high pixel density, direct conversion radiation detector substrate (30), with pixels (36) of the detector substrate in electrical connection to a corresponding pixel circuit (31) on an ASIC readout substrate (32),

the detector substrate providing for directly converting the impinging high energy x-ray gamma ray radiation (80) to an electrical charge and communicating the electrical charge via an electrical connection (35) between the pixel (36) to a corresponding pixel circuit on the ASIC readout substrate (32) as an electric charge signal, and

the pixel circuit, via the analog to digital converter, providing for processing the electric charge signal from each pixel into the pixel values with the first bit depth (N).

3. The system of claim 1, wherein,

the array of pixel values, where each pixel value has the first bit depth (N), at the output of the imaging device is un-corrected image pixel values, and

the processor calculates the final image pixel values (47) of the second bit depth (M) using a normalization module (24) that accumulates plural different frames of the first bit depth (N) to calculate each final image pixel value (47) of the second bit depth (M) to provide normalized, corrected image data determined from accumulated different frames of the first bit depth (N).

4. The system of claim 2, further comprising a high speed image frame processing module (18) in electronic communication with the ASIC readout substrate (32) of the imaging camera (37), the frame processing module receiving digitized pixel signals derived from a pixel circuit output from each pixel circuit (31) of the readout substrate and using the pixel signals to generate an image frame (44) at a frame readout rate of greater than ten image frames per second.

5. The system of claim 4, further comprising a calibration module selectably in digital communication with the frame processor module (18), the calibration module when selected being driven by a software process including a calibration routine (20) which calibration routine writes pixel correction data specific to each pixel (36) in an image frame (44) to a lookup table (22).

6. The system of claim 5, wherein the lookup table is writeable by the calibration module (20) with pixel specific correction data, and readable by a normalization module (24).

7. The system of claim 6, wherein the normalization module (24) is selectably in communication with the frame processor module (18) and with the lookup table (22), the normalization module receiving real time image frame data/record from the frame processor module and pixel specific correction data from the lookup table, and providing normalized image data comprising said final pixel values (47) via a display image output for use in a display module (16) to present said X-ray image.

8. The system of claim 7, wherein the processor calculates the final image pixel values (47) of the second bit depth (M) using a normalization module (24) to provide the final image pixel values (47) of the second bit depth (M) as normalized, corrected image data, said normalization module accumulating plural different frames of the first bit depth (N) to calculate each final image pixel value (47) of the second bit depth (M) to provide corrected image data determined from accumulated different frames of the first bit depth (N).

9. The system of claim 7, wherein the normalization module (24) provides said normalized image data via said display image output for use in said display module (16) to present a static X-ray image from the high energy, real time, direct detection X-ray imaging system (10).

10. The system of claim 9, wherein the normalization module (24) accumulates said normalized image data over a period of time to provide a high precision display image output for use in said display module (16) to present said static X-ray image.

11. The system of claim 8, wherein the normalization module (24) accumulates said normalized image data over a period of time of at least one hundredth of a second to ten seconds for providing a high precision display image output for each of the accumulation periods, for use in said display module (16) to present said dynamic X-ray image.

12. The system of claim 11, wherein the direct conversion radiation detector substrate comprises a Cadmium Telluride composition based radiation detector substrate (30) in communication with the ASIC readout substrate (32).

13. The system of claim 12, wherein the radiation detector substrate (30) consists of a composition selected from the group consisting of:

Cadmium-Telluride and Cadmium-Zinc-Telluride.

14. The system of claim 2, wherein the camera (37) includes a detector substrate bias switch circuit (121).

15. The system of claim 4, wherein the high speed image frame processing module (18) receives digitized pixel signals derived from the output of each pixel circuit (31) of the readout substrate (32) and uses the digitized pixel signals to generate an image frame (44) at a frame readout rate of greater than 25 image frames per second.

16. The system of claim 4, wherein the high speed image frame processing module (18) receives digitized pixel signals derived from the output from each pixel circuit (31) of the readout substrate (32) and uses the digitized pixel signals to generate an image frame (44) at a frame readout rate of greater than 50 image frames per second.

17. The system of claim 4, wherein the software process includes a calibration routine (20) which analyzes each of the digitized pixel values (47) over at least some of the collected calibration frames (44) being analyzed in accordance with a pixel value correction algorithm (49) to provide and write pixel value correction data specific to each pixel (36) in an image frame (44 ) to the lookup table (22).

18. The system of claim 5, wherein the software driving the calibration module (20) includes a pixel non-linear performance compensation routine (123) providing error correction for each pixel (36) as a function of time.

19. The system of claim 5, wherein the pixel non-linear performance compensation routine (123) includes an asymmetric linear polynomial calculation to determine correction coefficients to provide error correction for each pixel (36) as a function of time.