SEMICONDUCTOR DEVICE
1 Assignment
0 Petitions
Accused Products
Abstract
One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.
8 Citations
11 Claims
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1. (canceled)
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2. A semiconductor device comprising:
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a driver circuit comprising a plurality of pulse output circuits each comprising a first transistor, a second transistor and a third transistor each including an oxide semiconductor and a first signal line, a second signal line, and a third signal line, and a pixel portion, wherein a first terminal of the first transistor is electrically connected to the first signal line, wherein a second terminal of the first transistor is electrically connected to the third signal line, wherein a gate and a first terminal of the second transistor are electrically connected to the second signal line, and wherein a gate of the first transistor, a second terminal of the second transistor, and the first terminal of the third transistor are electrically connected to each other. - View Dependent Claims (3, 4, 5, 6)
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7. A semiconductor device comprising:
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a driver circuit comprising a plurality of pulse output circuits each comprising a first transistor, a second transistor and a third transistor each including a first oxide semiconductor and a first signal line, a second signal line, and a third signal line, and a pixel portion comprising a fourth transistor including a second oxide semiconductor, wherein a first terminal of the first transistor is electrically connected to the first signal line, wherein a second terminal of the first transistor is electrically connected to the third signal line, wherein a gate and a first terminal of the second transistor are electrically connected to the second signal line, and wherein a gate of the first transistor, a second terminal of the second transistor, and the first terminal of the third transistor are electrically connected to each other. - View Dependent Claims (8, 9, 10, 11)
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Specification