SEMICONDUCTOR DEVICE

• US 20130334533A1
• Filed: 06/12/2013
• Published: 12/19/2013
• Est. Priority Date: 06/15/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Granted Patent: US 9,153,699 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A transistor having high field-effect mobility is provided. In order that an oxide semiconductor layer through which carriers flow is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which carriers flow is separated from the gate insulating film is employed. Specifically, an oxide semiconductor layer having high conductivity is provided between two oxide semiconductor layers. Further, an impurity element is added to the oxide semiconductor layer in a self-aligned manner so that the resistance of a region in contact with an electrode layer is reduced. Further, the oxide semiconductor layer in contact with the gate insulating layer has a larger thickness than the oxide semiconductor layer having high conductivity.

Claims

1. A semiconductor device comprising:

an insulating layer over an insulating surface;

a first oxide semiconductor layer over the insulating layer;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a third oxide semiconductor layer over the second oxide semiconductor layer;

a gate insulating layer over the third oxide semiconductor layer; and

a gate electrode layer over the gate insulating layer,

wherein the second oxide semiconductor layer has higher conductivity than the third oxide semiconductor layer and the first oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein the second oxide semiconductor layer has a higher nitrogen concentration than the third oxide semiconductor layer and the first oxide semiconductor layer.

3. The semiconductor device according to claim 1,

wherein the second oxide semiconductor layer has a higher boron concentration than the third oxide semiconductor layer and the first oxide semiconductor layer.

4. The semiconductor device according to claim 1,

wherein the second oxide semiconductor layer has a higher phosphorus concentration than the third oxide semiconductor layer and the first oxide semiconductor layer.

5. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer has a larger thickness than the second oxide semiconductor layer and the third oxide semiconductor layer.

6. The semiconductor device according to claim 1, wherein a side surface of the second oxide semiconductor layer is covered with the third oxide semiconductor layer.

7. The semiconductor device according to claim 1, further comprising;

a source electrode layer in contact with the second oxide semiconductor layer; and

a drain electrode layer in contact with the second oxide semiconductor layer.

8. A semiconductor device comprising:

a first gate electrode layer over an insulating surface;

an insulating layer over the first gate electrode layer;

a first oxide semiconductor layer over the insulating layer;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a third oxide semiconductor layer over the second oxide semiconductor layer;

a source electrode layer in contact with the second oxide semiconductor layer;

a drain electrode layer in contact with the second oxide semiconductor layer;

a gate insulating layer over the third oxide semiconductor layer; and

a second gate electrode layer over the gate insulating layer,

wherein the second oxide semiconductor layer has higher conductivity than the third oxide semiconductor layer and the first oxide semiconductor layer.

9. The semiconductor device according to claim 8, wherein the second oxide semiconductor layer has a higher nitrogen concentration than the third oxide semiconductor layer and the first oxide semiconductor layer.

10. The semiconductor device according to claim 8,

wherein the second oxide semiconductor layer has a higher boron concentration than the third oxide semiconductor layer and the first oxide semiconductor layer.

11. The semiconductor device according to claim 8,

wherein the second oxide semiconductor layer has a higher phosphorus concentration than the third oxide semiconductor layer and the first oxide semiconductor layer.

12. The semiconductor device according to claim 8, wherein the first oxide semiconductor layer has a larger thickness than the second oxide semiconductor layer and the third oxide semiconductor layer.

13. The semiconductor device according to claim 8, wherein a side surface of the second oxide semiconductor layer is covered with the third oxide semiconductor layer.

14. A semiconductor device comprising:

a first insulating layer over an insulating surface;

a first oxide semiconductor layer over the first insulating layer;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a third oxide semiconductor layer over the second oxide semiconductor layer;

a second insulating layer on and in contact with the third oxide semiconductor layer;

a gate electrode layer over the second insulating layer; and

a third insulating layer on and in contact with the third oxide semiconductor layer,

wherein the second oxide semiconductor layer has a smaller thickness than the first oxide semiconductor layer and the third oxide semiconductor layer.

15. The semiconductor device according to claim 14,

wherein a region of the third oxide semiconductor layer which is in contact with the third insulating layer has low crystallinity and has a higher nitrogen concentration than a region of the third oxide semiconductor layer which is in contact with the second insulating layer, and

wherein the region of the third oxide semiconductor layer which is in contact with the second insulating layer overlaps with a channel formation region of the second oxide semiconductor layer.

16. The semiconductor device according to claim 14, wherein the third insulating layer is a silicon nitride film.

17. The semiconductor device according to claim 14, wherein the third insulating layer is a sidewall that is provided on a side surface of the gate electrode layer.

18. The semiconductor device according to claim 14, wherein a taper angle formed by an end surface of the first oxide semiconductor layer and a surface of the first insulating layer is greater than or equal to 10°

and less than or equal to 60°

.

19. The semiconductor device according to claim 14, wherein a taper angle formed by an end surface of the second oxide semiconductor layer and a surface of the first insulating layer is greater than or equal to 10°

and less than or equal to 60°

.

20. The semiconductor device according to claim 14, wherein a taper angle formed by an end surface of the third oxide semiconductor layer and a surface of the first insulating layer is greater than or equal to 10°

and less than or equal to 60°

.

21. The semiconductor device according to claim 14, wherein an end surface of the first oxide semiconductor layer and an end surface of the second oxide semiconductor layer are covered with the third oxide semiconductor layer.

22. The semiconductor device according to claim 14, further comprising a second gate electrode layer between the insulating surface and the first insulating layer.