SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

• US 20130334596A1
• Filed: 05/02/2013
• Published: 12/19/2013
• Est. Priority Date: 06/15/2012
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: HAN, Jin Woo
• Granted Patent: US 9,502,555 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes: a substrate comprising a trench; a first electrode disposed below the trench; a second electrode disposed above the trench, a first insulating layer being disposed between the first electrode and the second electrode; a first contact arranged in a first direction of the substrate and connected to the first electrode; and a second contact arranged in second direction that is different from the first direction, the second contact being connected to the second electrode.

Claims

1. A semiconductor device comprising:

a substrate comprising a trench;

a first electrode disposed below the trench;

a second electrode disposed above the trench, a first insulating layer being disposed between the first electrode and the second electrode;

a first contact arranged in a first direction of the substrate and connected to the first electrode; and

a second contact arranged in second direction that is different from the first direction, the second contact being connected to the second electrode.

2. The semiconductor of claim 1, further comprising a second insulating layer provided on a lower surface and on a sidewall of the trench.

3. The semiconductor of claim 1, wherein the first and second directions are perpendicular to each other.

4. The semiconductor device of claim 1, wherein the trench is formed by crossing of trenches.

5. The semiconductor device of claim 2, further comprising:

a third insulating layer formed on the second electrode;

a third electrode formed on the third insulating layer; and

a fourth electrode formed below the substrate.

6. The semiconductor device of claim 5, wherein the first electrode is a shield electrode, the second electrode is a gate electrode, the third electrode is a source electrode, and the fourth electrode is a drain electrode, and the shield electrode is configured to alter an electric field pattern inside the semiconductor device according to a voltage applied to the first contact.

7. The semiconductor device of claim 6, wherein the first and second contacts are metal patterns.

8. The semiconductor device of claim 4, wherein the first and third electrodes are electrically connected to each other.

9. The semiconductor device of claim 2, wherein the first electrode, located below the first contact, is formed on the substrate with the second insulating layer disposed between the substrate and the first electrode, and

the second electrode, located below the second contact, is formed on the substrate with the first insulating layer disposed between the substrate and the second electrode.

10. The semiconductor device of claim 1, wherein the first electrode, located below the first contact, does not overlapped with the second electrode, and

the second electrode, located below the second contact, does not overlapped with the first electrode.

11. The semiconductor device of claim 1, wherein the first and second electrodes comprise polysilicon.

12. A method for fabricating a semiconductor device, comprising:

providing a substrate comprising a trench;

forming a first electrode below the trench;

forming a first insulating layer on the first electrode;

forming a second electrode above the trench;

connecting a first contact that is arranged in a first direction of the substrate, to the first electrode; and

connecting a second contact that is arranged in a second direction different from the first direction, to the second electrode.

13. The method of claim 12, further comprising:

forming a second insulating layer on a lower surface and a sidewall of the trench and on the substrate before the forming of the first electrode.

14. The method of claim 12, wherein the first and second directions are perpendicular to each other.

15. The method of claim 12, wherein the trench is formed by crossing of trenches.

16. The method of claim 13, further comprising:

forming a third insulating layer on the second electrode;

forming a third electrode on the third insulating layer; and

forming a fourth electrode on a lower portion of the substrate.

17. The method of claim 16, wherein the first electrode is a shield electrode, the second electrode is a gate electrode, the third electrode is a source electrode, and the fourth electrode is a drain electrode, and

the shield electrode is configured to alter an electric field pattern inside the semiconductor device according to a voltage applied to the first contact.

18. The method of claim 16, wherein the first and third electrodes are electrically connected to each other.

19. The method of claim 12, wherein the first and second contacts are made from a same material.

20. The method of claim 12, wherein the first electrode, located below the first contact, is formed on the substrate with the second insulating layer disposed between the substrate and the first electrode, and

the second electrode, located below the second contact, is formed on the substrate with the first insulating layer disposed between the substrate and the second electrode.

21. The method of claim 12, wherein the first and second electrodes comprise polysilicon.

22. The method of claim 12, wherein the connecting of the first contact to the first electrode is performed concurrently with the connecting of the second contact to the second electrode.

23. An MOS transistor comprising:

a trench disposed in a substrate;

a first electrode disposed in a lower portion of the trench;

a second electrode disposed in an upper portion of the trench, the first and the second electrodes separated by an insulating layer;

a first contact that extends in a first direction of the substrate and connects to the first electrode; and

a second contact that extends in a second direction that is different from the first direction and connects to the second electrode.