POWER SEMICONDUCTOR DEVICE

• US 20130334597A1
• Filed: 12/19/2012
• Published: 12/19/2013
• Est. Priority Date: 06/13/2012
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamashita, Hiroaki, Ohta, Hiroshi, Izumisawa, Masaru, Ono, Syotaro
• Application Number:
  US13/720,344
• Publication Number:
  US 20130334597A1
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0856 Source regions
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type having an effective impurity concentration that is less than an effective impurity concentration of the first semiconductor layer arranged on the first semiconductor layer, a third semiconductor layer of a second conductivity type arranged on the second semiconductor layer, and a gate electrode formed in the first second semiconductor layer and the third semiconductor layer, wherein at least two regions are formed in the power semiconductor device, and a threshold voltage of the first region is different from a threshold voltage of the second region.

Claims

1. A power semiconductor device, comprising:

a first semiconductor layer having a first conductivity type;

a second semiconductor layer having the first conductivity type disposed on the first semiconductor layer, the first semiconductor layer having an effective impurity concentration that is greater than an effective impurity concentration of the second semiconductor layer;

a third semiconductor layer having a second conductivity type that is different from the first conductivity type;

a fourth semiconductor layer comprising a plurality of semiconductor layers having the first conductivity type and the second conductivity type; and

a first gate electrode formed between adjacent semiconductor layers of the fourth semiconductor layer, the adjacent layers having the first conductivity type, and the first gate electrode extending to the second semiconductor layer through the third semiconductor layer,

wherein at least two regions are formed in the power semiconductor device, and each of the regions is formed to have a different threshold voltage.

2. The power semiconductor device of claim 1, wherein the at least two regions are formed to have different threshold voltages by varying a thickness of the third semiconductor layer.

3. The power semiconductor device of claim 1, wherein the at least two regions are formed to have different threshold voltages by varying an effective impurity concentration of the third semiconductor layer.

4. The power semiconductor device of claim 1, wherein the first gate electrode and the first, second, third, and fourth semiconductor layers comprise parts of a first transistor.

5. The power semiconductor device of claim 4, further comprising:

a junction layer disposed through the third semiconductor layer to separate portions of the fourth semiconductor layer, the junction layer comprising a protruded portion of the second semiconductor layer.

6. The power semiconductor device of claim 5, wherein a second gate electrode is formed on the junction layer, the second gate electrode comprises a part of a second transistor.

7. The power semiconductor device of claim 6, wherein the second gate electrode is formed as a mesh having a plurality of elliptical shapes.

8. The power semiconductor device of claim 6, wherein the second gate electrode is formed as a mesh having a plurality of octagonal shapes.

9. The power semiconductor device of claim 6, further comprising:

a variable conductivity layer formed in the third semiconductor layer between the junction layer and the second gate electrode.

10. A power semiconductor device, comprising:

a drain electrode and a source electrode having a semiconductor portion disposed therebetween, wherein the semiconductor portion comprises;

a drain layer having a first conductivity type;

a drift layer having the first conductivity type disposed on the drain layer, the drain layer having an effective impurity concentration that is greater than an effective impurity concentration of the drift layer;

abase layer having a second conductivity type that is different than the first conductivity type;

a semiconductor layer comprising a plurality of source layers having the first conductivity type and a plurality of contact layers having the second conductivity type; and

a first gate electrode formed between adjacent source layers of the semiconductor layer, the first gate electrode extending to the drift layer through the base layer, wherein at least two regions are formed in the semiconductor portion with different effective impurity concentration of the base layer and the source layers.

11. The power semiconductor device of claim 10, wherein the at least two regions have different threshold voltages.

12. The power semiconductor device of claim 10, wherein the at least two regions have different channel lengths.

13. The power semiconductor device of claim 10, wherein the first gate electrode and the drain layer, the drift layer, the base layer, the source layers and the contact layers comprise parts of a first transistor.

14. The power semiconductor device of claim 13, further comprising:

a junction layer disposed through the base layer to separate portions of the source layers, the junction layer comprising a protruded portion of the second semiconductor layer.

15. The power semiconductor device of claim 14, wherein a second gate electrode is formed in the junction layer, the second gate electrode comprising a part of a second transistor.

16. The power semiconductor device of claim 14, wherein the second gate electrode is formed as a mesh having a plurality of elliptical shapes.

17. The power semiconductor device of claim 14, wherein the second gate electrode is formed as a mesh having a plurality of octagonal shapes.

18. The power semiconductor device of claim 14, further comprising:

a variable conductivity layer disposed in the third semiconductor layer between the junction layer and the second gate electrode.

19. A method for manufacturing a power semiconductor device, the method comprising:

forming a first layer having a first conductivity type;

forming a second layer on the first layer, the second layer having the first conductivity type, wherein the first layer has an effective impurity concentration that is greater than an effective impurity concentration of the second layer;

forming a third layer on the second layer, the third layer having a second conductivity type that is different than the first conductivity type;

forming a fourth layer comprising a plurality of semiconductor layers having the first conductivity type and the second conductivity type; and

forming a first transistor between adjacent semiconductor layers of the fourth layer, the adjacent layers having the first conductivity type, and the first gate electrode extending to the second layer through the third layer, wherein at least two regions are formed in the power semiconductor device, and each of the regions has a different threshold voltage.

20. The method of claim 19, further comprising:

forming a junction layer on the third layer, the junction layer comprising a protruded portion of the second semiconductor layer to form a second transistor.