SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

• US 20130334598A1
• Filed: 03/18/2013
• Published: 12/19/2013
• Est. Priority Date: 06/13/2012
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: OKUMURA, Hideki
• Application Number:
  US13/846,761
• Publication Number:
  US 20130334598A1
• Time in Patent Office: Days
• US Class Current: 257/335
• CPC Class Codes: H01L 29/0607 for preventing surface leakage or controlling electric field concentration
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66 Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes first to fourth semiconductor layers, a gate electrode, a field plate electrode, an insulating film, first and second main electrodes, and an insulating section. The second semiconductor layer has the first conductivity type and is provided on the first semiconductor layer. The third semiconductor layer has a second conductivity type and is provided on the second semiconductor layer. A concentration of impurity of the first conductivity type included in the third semiconductor layer is lower than the concentration of impurity of the first conductivity type included in the second semiconductor layer. The fourth semiconductor layer is provided on the third semiconductor layer. The gate electrode extends from the fourth semiconductor layer toward the second semiconductor layer. The field plate electrode is provided below the gate electrode.

Claims

1. A semiconductor device comprising:

a first semiconductor layer having a first conductivity type;

a second semiconductor layer having the first conductivity type and provided on the first semiconductor layer, a concentration of impurity of the first conductivity type included in the second semiconductor layer being lower than a concentration of impurity of the first conductivity type included in the first semiconductor layer;

a third semiconductor layer having a second conductivity type and provided on the second semiconductor layer, the third semiconductor layer having a first portion and a second portion surrounding the first portion in a plane perpendicular to stacking direction of the first semiconductor layer and the second semiconductor layer, a concentration of impurity of the first conductivity type included in the third semiconductor layer being lower than the concentration of impurity of the first conductivity type included in the second semiconductor layer;

a fourth semiconductor layer having the first conductivity type and provided on the first portion;

a gate electrode extending from the fourth semiconductor layer toward the second semiconductor layer and having a lower end located in the second semiconductor layer;

a field plate electrode provided below the gate electrode and having a lower end located in the second semiconductor layer;

an insulating film provided between the gate electrode and the fourth semiconductor layer, between the gate electrode and the first portion, between the gate electrode and the second semiconductor layer, between the gate electrode and the field plate electrode, and between the field plate electrode and the second semiconductor layer;

a first main electrode electrically connected to the first semiconductor layer;

a second main electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer; and

an insulating section provided at least between the first portion and the second portion and electrically insulating between the first portion and the second portion.

2. The device according to claim 1, further comprising:

a first ohmic contact layer having the second conductivity type and penetrating through the fourth semiconductor layer to the third semiconductor layer and being in ohmic contact with the second main electrode.

3. The device according to claim 2, wherein impurity concentration of the first ohmic contact layer is higher than impurity concentration of the third semiconductor layer.

4. The device according to claim 1, wherein the second portion is electrically connected to the first main electrode.

5. The device according to claim 4, further comprising:

an outer peripheral electrode provided on the second portion and electrically connected to the first main electrode and the second portion.

6. The device according to claim 5, further comprising:

a second ohmic contact layer having the second conductivity type and provided in the second portion and being in ohmic contact with the outer peripheral electrode, impurity concentration of the second ohmic contact layer being higher than impurity concentration of the third semiconductor layer.

7. The device according to claim 1, wherein the third semiconductor layer has a pillar section extending from the first portion toward the first semiconductor layer.

8. The device according to claim 7, wherein effective dose amount (in units of atoms/cm²) of impurity of the second conductivity type per unit area in a flat plane parallel to the plane of the pillar section is denoted by N1, effective dose amount (in units of atoms/cm²) of impurity of the first conductivity type per unit area in a flat plane parallel to the plane of an opposed region of the second semiconductor layer opposed to the pillar section in a direction parallel to the plane is denoted by N2, and the N1 and the N2 satisfy a relation of 1≦

(2×

N2)/N1≦

1.5.

9. The device according to claim 1, wherein the first main electrode includes at least one of V, Ni, Au, Ag, and Sn.

10. The device according to claim 1, wherein the second main electrode includes Al.

11. The device according to claim 1, further comprising:

an interlayer insulating film provided between the second main electrode and the gate electrode and electrically insulating between the second main electrode and the gate electrode.

12. The device according to claim 1, wherein the field plate electrode is electrically connected to the second main electrode.

13. The device according to claim 1, wherein

the second semiconductor layer has a first side surface along the stacking direction,

the second portion of the third semiconductor layer has a second side surface along the stacking direction, and

the second side surface is located in a same plane as the first side surface.

14. The device according to claim 13, wherein the first side surface and the second side surface are crushed layers.

15. The device according to claim 1, wherein

the third semiconductor layer includes a low rate-of-change region having a low rate of change of concentration of impurity of the second conductivity type with respect to the stacking direction, and

a maximum concentration in the low rate-of-change region is denoted by Pmax, a minimum concentration in the low rate-of-change region is denoted by Pmin, and ratio Pmax/Pmin of the Pmax to the Pmin is 5 or less.

16. The device according to claim 15, wherein the low rate-of-change region extends in the fourth semiconductor layer.

17. The device according to claim 1, wherein a potential of the second portion is a floating potential.

18. A method for manufacturing a semiconductor device, comprising:

forming a workpiece by forming a second semiconductor film on a major surface of a first semiconductor substrate having a first conductivity type, the second semiconductor film having a lower impurity concentration than the first semiconductor substrate, and by forming a third semiconductor film having a second conductivity type on the second semiconductor film by epitaxial growth, the workpiece including the first semiconductor substrate, the second semiconductor film, and the third semiconductor film and having a device region and a termination region surrounding the device region in a plane parallel to the major surface;

forming a gate trench penetrating through the third semiconductor film to part of the second semiconductor film in the device region, and a termination trench penetrating through the third semiconductor film to part of the second semiconductor film at a boundary between the device region and the termination region;

forming a first insulating layer on an inner wall surface of the gate trench and the termination trench;

forming a field plate electrode in a portion of the gate trench below the third semiconductor film by embedding a conductive material in a remaining space in the gate trench;

removing a portion of the first insulating layer above the field plate electrode;

forming a second insulating layer above the field plate electrode in the gate trench and on the inner wall surface of the gate trench above the field plate electrode, and forming a gate electrode by embedding a conductive material in a remaining space in the gate trench; and

selectively doping an upper portion of the device region of the third semiconductor film with impurity of the first conductivity type.

19. The method according to claim 18, wherein

the forming a second semiconductor film includes forming a pillar trench extending along a first direction parallel to the major surface in the second semiconductor film in the device region,

the forming a third semiconductor film includes forming a pillar section extending toward the first semiconductor substrate in the third semiconductor film by embedding the third semiconductor film inside the pillar trench, and

the forming a gate trench includes forming first and second gate trenches extending along the first direction and spaced from the pillar section in a second direction parallel to the major surface and perpendicular to the first direction, the pillar section being placed between the first gate trench and the second gate trench.

20. The method according to claim 18, wherein

the forming a workpiece includes, after forming the second semiconductor film, forming a pillar section extending toward the first semiconductor substrate by selectively doping a portion of the device region of the second semiconductor film with impurity of the second conductivity type, and

the forming a gate trench includes forming first and second gate trenches extending along the first direction and spaced from the pillar section in a second direction parallel to the major surface and perpendicular to the first direction, the pillar section being placed between the first gate trench and the second gate trench.