ELECTRONIC DEVICE PACKAGES HAVING BUMPS AND METHODS OF MANUFACTURING THE SAME
First Claim
Patent Images
1. An electronic device package comprising:
- a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post;
an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and
a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip.
1 Assignment
0 Petitions
Accused Products
Abstract
An electronic device package includes a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip.
11 Citations
20 Claims
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1. An electronic device package comprising:
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a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip. - View Dependent Claims (2, 3, 4)
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5. An electronic device package comprising:
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a semiconductor chip mounted on a bottom dielectric layer; a bump having a post disposed on a contact portion of the semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; a dielectric layer embedding the semiconductor chip and exposing the enlarged portion of the bump and an upper sidewall of the post; and an interconnection portion having a locking portion that substantially surrounds the enlarged portion of the bump and the upper sidewall of the post and a connecting portion that extends from the locking portion onto the dielectric layer.
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6. A method of manufacturing an electronic device package, the method comprising:
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forming a first dielectric layer that substantially surrounds a semiconductor chip having a contact portion, the first dielectric layer having an opening that exposes an upper sidewall of a post disposed on the contact portion and exposes an enlarged portion laterally protruded from an upper portion of the post; and forming an interconnection portion including a locking portion that substantially surrounds the enlarged portion and the exposed upper sidewall of the post, wherein the post and the enlarged portion constitute a bump and the interconnection portion is formed to extend onto the first dielectric layer. - View Dependent Claims (7)
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8. A method of manufacturing an electronic device package, the method comprising:
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forming a post on a contact portion of a semiconductor chip; forming a first dielectric layer substantially covering the semiconductor chip; removing a portion of the first dielectric layer to form an opening that exposes an upper portion of the post; forming an enlarged portion that is disposed on the post to laterally protrude from a sidewall of the post; and forming an interconnection portion on the first dielectric layer, wherein the interconnection portion is formed to have a locking portion that substantially fills the opening to substantially cover the enlarged portion and an upper sidewall of the post, and the post and the enlarged portion constitute a bump. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method of manufacturing an electronic device package, the method comprising:
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forming a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; forming a dielectric layer on the semiconductor chip; removing a portion of the dielectric layer to form an opening that exposes the enlarged portion and an upper sidewall of the post under the enlarged portion; and forming an interconnection portion on the dielectric layer, wherein the interconnection portion is formed to have a locking portion that substantially fills the opening to substantially cover the enlarged portion and the upper sidewall of the post. - View Dependent Claims (19, 20)
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Specification