SUBSTRATE STRUCTURE AND PACKAGE STRUCTURE

• US 20130334684A1
• Filed: 10/18/2012
• Published: 12/19/2013
• Est. Priority Date: 06/19/2012
• Status: Abandoned Application

• Current Assignee: Siliconware Precision Industries Co., Ltd.
• Original Assignee: Siliconware Precision Industries Co., Ltd.
• Inventors: Lin, Chang-Fu, Chen, Chin-Te, Yao, Chin-Tsai
• Application Number:
  US13/654,780
• Publication Number:
  US 20130334684A1
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/82385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/3841 Solder bridging

Abstract

A substrate structure is provided, including a substrate body and a plurality of traces formed on a surface of the substrate body. At least one of the traces has an electrical contact formed in a groove thereof for electrically connecting an external element, thereby meeting the demands of fine line/fine pitch and miniaturization and improving the product yield.

Claims

1. A substrate structure, comprising:

a substrate body; and

a plurality of traces formed on a surface of the substrate body, at least one of the traces having an electrical contact for electrically connecting an external element, wherein the electrical contact is formed with a groove.

2. The substrate structure of claim 1, wherein the groove is a trace broken section for a portion of the surface of the substrate body to be exposed therefrom.

3. The substrate structure of claim 1, wherein the substrate body is a packaging substrate or a circuit board.

4. A package structure, comprising:

a substrate body;

a plurality of traces formed on a surface of the substrate body, at least one of the traces having an electrical contact for electrically connecting an external element, wherein the electrical contact is formed with a groove; and

a semiconductor chip having a plurality of electrode pads formed on a surface thereof and disposed on the substrate body via the surface having the electrode pads, wherein a conductive bump is formed on each of the electrode pads and has an end portion extended into the groove of a corresponding one of the traces and electrically connected to the corresponding one of the traces.

5. The substrate structure of claim 4, wherein the groove is a trace broken section for a portion of the surface of the substrate body to be exposed therefrom.

6. The substrate structure of claim 4, wherein the end portion of the conductive bump is connected to the trace broken section of the at least one of the traces.

7. The substrate structure of claim 4, wherein the conductive bump comprises a metal post and a solder material formed on one end of the metal post and disposed in the groove of the corresponding one of the traces.

8. The substrate structure of claim 4, wherein the conductive bump is made of a solder material.

9. The substrate structure of claim 4, further comprising an underfill formed between the semiconductor chip and the substrate body.

10. The substrate structure of claim 4, further comprising an insulation layer formed on the surface of the semiconductor chip and having a plurality of openings for exposing the electrode pads.

11. The substrate structure of claim 4, further comprising an under bump metallurgy layer formed between the conductive bump and the corresponding electrode pad.

12. The substrate structure of claim 4, wherein the substrate body is a packaging substrate or a circuit board.