SEMICONDUCTOR MEMORY DEVICE
First Claim
1. A semiconductor memory device, comprising a memory cell including:
- a first driving transistor connected to a first storage node;
a first load transistor connected to the first storage node;
a first read transfer transistor connected between the first storage node and a first read bit line;
a first variable resistance element which has one terminal connected to the first storage node and has the other terminal, a resistance of which changes depending on a voltage applied to both terminals;
a first write transfer transistor arranged between a first write bit line and the first variable resistance element;
a second driving transistor connected to a second storage node;
a second load transistor connected to the second storage node;
a second read transfer transistor arranged between the second storage node and a second read bit line;
a second write transfer transistor arranged between the second storage node and a second write bit line.
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Accused Products
Abstract
According to one embodiment, there is provided a semiconductor memory device including a memory cell. The memory cell includes a first driving transistor, a first load transistor, a first read transfer transistor, a first write transfer transistor, a second driving transistor, a second load transistor, a second read transfer transistor, a second write transfer transistor, and one or more variable resistance elements. The one or more variable resistance elements has resistance that changes depending on a direction of a bias applied to both terminals. The one or more variable resistance elements are arranged in at least one of a portion between a first storage node and a first write transfer transistor and a portion between a second storage node and a second write transfer transistor.
13 Citations
13 Claims
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1. A semiconductor memory device, comprising a memory cell including:
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a first driving transistor connected to a first storage node; a first load transistor connected to the first storage node; a first read transfer transistor connected between the first storage node and a first read bit line; a first variable resistance element which has one terminal connected to the first storage node and has the other terminal, a resistance of which changes depending on a voltage applied to both terminals; a first write transfer transistor arranged between a first write bit line and the first variable resistance element; a second driving transistor connected to a second storage node; a second load transistor connected to the second storage node; a second read transfer transistor arranged between the second storage node and a second read bit line; a second write transfer transistor arranged between the second storage node and a second write bit line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification