REDUCING PENALTIES FOR CACHE ACCESSING OPERATIONS

• US 20130339593A1
• Filed: 06/14/2012
• Published: 12/19/2013
• Est. Priority Date: 06/14/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Fee, Michael F., Jones, Christine C., O'Neill, Arthur J., Orf, Diane L.
• Granted Patent: US 9,075,727 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 12/0846 Cache with multiple tag or data arrays being simultaneously accessible
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer program product for reducing penalties for cache accessing operations is provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes respectively associating platform registers with cache arrays, loading control information and data of a store operation to be executed with respect to one or more of the cache arrays into the one or more of the platform registers respectively associated with the one or more of the cache arrays, and, based on the one or more of the cache arrays becoming available, committing the data from the one or more of the platform registers using the control information from the same platform registers to the one or more of the cache arrays.

Claims

1. A computer program product for reducing penalties for cache accessing operations, the computer program product comprising:

a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

respectively associating platform registers with cache arrays;

loading control information and data of a store operation to be executed with respect to one or more of the cache arrays into the one or more of the platform registers respectively associated with the one or more of the cache arrays, the loading being conducted by way of a coupling between a pipe passage through which the store operation is proceeding and the one or more of the platform registers; and

based on the one or more of the cache arrays becoming available, committing the data from the one or more of the platform registers using the control information from the same platform registers to the one or more of the cache arrays.

2. The computer program product according to claim 1, wherein the platform registers are disposed proximate to the respectively associated cache arrays, wherein the cache arrays comprise dynamic random access memory (DRAM) or embedded dynamic random access memory (eDRAM).

3. The computer program product according to claim 1, wherein the method further comprises:

receiving an instruction to execute the store operation;

analyzing the store operation; and

identifying the one or more of the cache arrays with respect to which the store operation is to be executed in accordance with results of the analyzing.

4. The computer program product according to claim 1, wherein the control information comprises addresses and identification information of the one or more of the cache arrays.

5. The computer program product according to claim 1, wherein the method further comprises determining that the one or more of the cache arrays is available, and the determining is conducted with the control information loaded into the one or more of the platform registers.

6. The computer program product according to claim 1, wherein the method further comprises:

completing the committing of the data using the control information; and

making the one or more of the platform registers available for other store operations.

7. A system for reducing penalties for cache accessing operations, the system comprising:

cache arrays and platform registers respectively associated with the cache arrays, the system configured to perform a method comprising;

loading control information and data of a store operation to be executed with respect to one or more of the cache arrays into the one or more of the platform registers respectively associated with the one or more of the cache arrays, the loading being conducted by way of a coupling between a pipe passage through which the store operation is proceeding and the one or more of the platform registers; and

based on the one or more of the cache arrays becoming available, committing the data from the one or more of the platform registers using the control information from the same platform registers to the one or more of the cache arrays.

8. The system according to claim 7, wherein the platform registers are disposed proximate to the respectively associated cache arrays.

9. The system according to claim 8, wherein the cache arrays comprise dynamic random access memory (DRAM) or embedded dynamic random access memory (eDRAM).

10. The system according to claim 7, wherein the method further comprises:

receiving an instruction to execute the store operation;

analyzing the store operation; and

identifying the one or more of the cache arrays with respect to which the store operation is to be executed in accordance with results of the analyzing.

11. The system according to claim 7, wherein the control information comprises addresses and identification information of the one or more of the cache arrays.

12. The system according to claim 7, wherein the method further comprises determining that the one or more of the cache arrays is available.

13. The system according to claim 12, wherein the determining is conducted with the control information loaded into the one or more of the platform registers.

14. The system according to claim 7, wherein the method further comprises:

completing the committing of the data using the control information; and

making the one or more of the platform registers available for other store operations.

15. A computer implemented method for reducing penalties for cache accessing operations, the method comprising:

respectively associating platform registers with cache arrays;

loading control information and data of a store operation to be executed with respect to one or more of the cache arrays into the one or more of the platform registers respectively associated with the one or more of the cache arrays, the loading being conducted by way of a coupling between a pipe passage through which the store operation is proceeding and the one or more of the platform registers; and

based on the one or more of the cache arrays becoming available, committing the data from the one or more of the platform registers using the control information from the same platform arrays to the one or more of the cache arrays.

16. The computer implemented method according to claim 15, wherein the platform registers are disposed proximate to the respectively associated cache arrays, and wherein the cache arrays comprise dynamic random access memory (DRAM) or embedded dynamic random access memory (eDRAM).

17. The computer implemented method according to claim 15, further comprising:

receiving an instruction to execute the store operation;

analyzing the store operation; and

identifying the one or more of the cache arrays with respect to which the store operation is to be executed in accordance with results of the analyzing.

18. The computer implemented method according to claim 15, wherein the control information comprises addresses and identification information of the one or more of the cache arrays.

19. The computer implemented method according to claim 15, further comprising determining that the one or more of the cache arrays is available, the determining being conducted with the control information loaded into the one or more of the platform registers.

20. The computer implemented method according to claim 15, further comprising:

completing the committing of the data using the control information; and

making the one or more of the platform registers available for other store operations.