IDENTIFYING AND PRIORITIZING CRITICAL INSTRUCTIONS WITHIN PROCESSOR CIRCUITRY

• US 20130339595A1
• Filed: 12/30/2011
• Published: 12/19/2013
• Est. Priority Date: 12/30/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Subramoney, Sreenivas, Kumar, Amit
• Granted Patent: US 9,323,678 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating

Abstract

In one embodiment, the present invention includes a method for identifying a memory request corresponding to a load instruction as a critical transaction if an instruction pointer of the load instruction is present in a critical instruction table associated with a processor core, sending the memory request to a system agent of the processor with a critical indicator to identify the memory request as a critical transaction, and prioritizing the memory request ahead of other pending transactions responsive to the critical indicator. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a first core to execute instructions, the first core including a pipeline having a reorder buffer (ROB) including a plurality of entries each associated with an instruction received in the pipeline, and a critical instruction logic to determine whether a load instruction is a critical instruction and if so to send a memory request transaction associated with the load instruction to a system agent of the processor with a critical indicator to indicate the critical instruction; and

the system agent coupled to the first core and including a distributed cache controller having a plurality of portions each associated with a corresponding portion of a distributed shared cache memory, a memory controller to interface with a system memory coupled to the processor, and an interconnect to couple the distributed shared cache memory and the distributed cache controller with the first core, wherein the system agent is to prioritize the memory request transaction when indicated to be a critical instruction.

2. The processor of claim 1, wherein the system agent comprises a first arbiter associated with the interconnect, the first arbiter to prioritize the memory request transaction including the critical indicator ahead of at least one other transaction present in a buffer to store pending transactions for insertion onto the interconnect.

3. The processor of claim 2, wherein the system agent comprises a second arbiter associated with the distributed cache controller, the second arbiter to prioritize the memory request transaction including the critical indicator ahead of at least one other transaction that seeks access to the distributed shared cache memory.

4. The processor of claim 3, wherein the system agent comprises a third arbiter associated with the memory controller, the third arbiter to prioritize the memory request transaction including the critical indicator ahead of at least one other transaction that seeks access to the system memory.

5. The processor of claim 1, wherein the critical instruction logic is to insert an instruction pointer of the load instruction in an entry of a critical instruction table when the load instruction is identified as a critical instruction.

6. The processor of claim 5, wherein the critical instruction logic is to access the critical instruction table to determine whether a second load instruction is a critical instruction and to identify the second load instruction as a critical instruction if an entry of the critical instruction table is associated with the second load instruction.

7. The processor of claim 5, wherein the critical instruction logic is to identify the load instruction as a critical instruction when data associated with the load instruction is not present in at least one core cache of the first core and a dependency counter field of an entry of the ROB associated with the load instruction is greater than a threshold.

8. The processor of claim 7, wherein the dependency counter field of the entry is to be updated when a source operand of a first instruction corresponds to a destination operand of the load instruction.

9. The processor of claim 8, wherein the dependency counter field of the entry is to be updated when a source operand of a second instruction corresponds to a destination operand of the first instruction.

10. The processor of claim 7, wherein the critical instruction logic is to set a miss indicator of the ROB entry when the data associated with the load instruction is not present in a first and a second cache of the first core.

11. The processor of claim 1, wherein the system agent is to prioritize a second transaction over at least one other pending transaction based on an identification of an originating core of the processor.

12. The processor of claim 11, wherein the system agent is to prioritize the second transaction corresponding to a latency-sensitive request from the first core over a third transaction corresponding to a bandwidth-sensitive request from a graphics engine of the processor.

13. A method comprising:

identifying, in a first core of a processor, a memory request corresponding to a load instruction as a critical transaction if an instruction pointer of the load instruction is present in a critical instruction table of the first core;

sending the memory request to a system agent of the processor with a critical indicator to identify the memory request as a critical transaction; and

prioritizing the memory request ahead of a plurality of pending transactions in the system agent responsive to the critical indicator.

14. The method of claim 13, further comprising prioritizing the memory request onto an interconnect of the system agent ahead of at least one other transaction seeking access to the interconnect.

15. The method of claim 14, further comprising prioritizing lookup for the memory request in a shared cache memory of the system agent ahead of at least one other transaction seeking access to the shared cache memory.

16. The method of claim 15, further comprising:

prioritizing a communication associated with the memory request from a memory controller of the system agent to a system memory coupled to the processor to obtain data for the memory request ahead of at least one other transaction seeking access to the system memory; and

prioritizing return of the data to the first core ahead of at least one other transaction seeking to communicate with the first core.

17. The method of claim 13, further comprising identifying the load instruction as a critical instruction and storing the instruction pointer and metadata associated with the load instruction in the critical instruction table if a dependency counter field of an entry of a reorder buffer (ROB) associated with the load instruction is greater than a threshold and a miss indicator of the reorder buffer entry is set.

18. The method of claim 17, further comprising not storing the instruction pointer and the metadata in the critical instruction table if a ratio of a number of load instructions stored in the critical instruction table to a total number of unique load instructions is greater than a ratio threshold.

19. A system comprising:

a multicore processor including a first core to execute instructions, the first core including a pipeline, a first cache memory and a critical instruction logic to identify an instruction as a critical instruction based on a criticality level and a delinquency level associated with the instruction, and a system agent including a cache controller to control access to a shared cache memory and a memory controller to interface with a dynamic random access memory (DRAM) coupled to the multicore processor, wherein the cache controller and the memory controller are to prioritize fulfillment of a memory request having a critical indicator ahead of at least one other memory request not having the critical indicator; and

the DRAM coupled to the multicore processor.

20. The system of claim 19, wherein the system agent comprises a first arbiter associated with an interconnect of the system agent to prioritize the memory request having the critical indicator, a second arbiter associated with the cache controller to prioritize the memory request having the critical indicator and a third arbiter associated with the memory controller to prioritize the memory request having the critical indicator.

21. The system of claim 20, wherein the critical instruction logic is to identify the instruction as a critical instruction when a metadata field of a reorder buffer (ROB) entry associated with the instruction is greater than a first threshold and the instruction misses in at least one cache memory of the first core.

22. The system of claim 21, wherein the critical instruction logic is to store an instruction pointer of the instruction in a critical instruction table when the metadata field of the ROB entry is greater than the first threshold and the instruction misses in the at least one cache memory.