REDUCING STORE OPERATION BUSY TIMES

• US 20130339607A1
• Filed: 03/08/2013
• Published: 12/19/2013
• Est. Priority Date: 06/14/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: BERGER, DEANNA POSTLES DUNN, FEE, MICHAEL F., JONES, CHRISTINE C., O'NEILL, ARTHUR J., ORF, DIANE L.
• Granted Patent: US 9,037,806 B2
• Time in Patent Office: Days
• US Class Current: 711/119
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G11C 2207/229 Timing of a write operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer product for reducing store operation busy times is provided. The computer product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes associating first and second platform registers with a cache array, determining that first and second store operations target a same wordline of the cache array, loading control information and data of the first and second store operation into the first and second platform registers and delaying a commit of the first store operation until the loading of the second platform register is complete. The method further includes committing the data from the first and second platform registers using the control information from the first and second platform registers to the wordline of the cache array at a same time to thereby reduce a busy time of the wordline of the cache array.

Claims

1. A computer implemented method for reducing store operation busy times, the method comprising:

associating first and second platform registers with a cache array;

determining, by a comparator, that a first store operation targets a wordline of the cache array;

determining, by the comparator, that a second store operation targets the same wordline of the cache array;

loading control information and data of the first and second store operation into the first and second platform registers;

delaying, by a buffer, a commit of the first store operation until the control information and data of the second store operation is loaded into the second platform register; and

committing the data from the first and second platform registers using the control information from the first and second platform registers to the wordline of the cache array at a same time to thereby reduce a busy time of the wordline of the cache array.

2. The method according to claim 1, wherein the first platform register comprises a primary platform register and the second platform register comprises an alternate platform register.

3. The method according to claim 1, further comprising associating multiple alternate platform registers with the cache array.

4. The method according to claim 1, further comprising activating the wordline of the cache array once for the first and second store operations.

5. The method according to claim 1, wherein the determining that the first store operation targets a wordline of the cache array and the determining that the second store operation targets the same wordline of the cache array comprise comparing the first and second store operations, and wherein the comparing of the first and second store operations comprises comparing store operation addresses of the first and second store operations.

6. The method according to claim 1, further comprising issuing a delay signal based on a determination that the first and second store operations target a same wordline of the cache array.