Radix Table Translation of Memory

• US 20130339652A1
• Filed: 06/14/2012
• Published: 12/19/2013
• Est. Priority Date: 06/14/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bybell, Anthony J., Gschwind, Michael K.
• Granted Patent: US 9,811,472 B2
• Time in Patent Office: Days
• US Class Current: 711/206
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1018 involving hashing techniques, e.g. inverted page tables
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence

Abstract

Embodiments relate to managing memory page tables in a processing system. A request to access a desired block of memory is received. The request includes an effective address that includes an effective segment identifier (ESID) and a linear address, the linear address including a most significant portion and a byte index. An entry in a buffer that includes the ESID of the effective address is located. Based on the entry including a radix page table pointer (RPTP), performing: using the RPTP to locate a translation table of a hierarchy of translation tables, using the located translation table to translate the most significant portion of the linear address to obtain an address of a block of memory, and based on the obtained address, performing the requested access to the desired block of memory.

Claims

1. A computer program product for accessing a memory location in a processing system, the computer program product comprising:

a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

receiving a request to access a desired block of memory, the request comprising an effective address that includes an effective segment identifier (ESID) and a linear address, the linear address comprising a most significant portion and a byte index;

locating, by a processor, an entry, in a buffer, the entry including the ESID of the effective address; and

based on the entry including a radix page table pointer (RPTP), performing;

using the RPTP to locate a translation table of a hierarchy of translation tables;

using the located translation table to translate the most significant portion of the linear address to obtain an address of a block of memory; and

based on the obtained address, performing the requested access to the desired block of memory.

2. The computer product of claim 1, wherein based on the entry including a VSID, performing locating a page table entry of a group of translation table entries using a hash function to obtain an address of a block of memory.

3. The computer product of claim 1, wherein the using the obtained address comprises using the byte index of the linear address and the obtained address to form an address of the desired block of memory.

4. The computer product of claim 1, wherein the table level of the located translation table of the hierarchy of translation tables is indicated by the RPTP.

5. The computer product of claim 1, wherein the RPTP specifies size of the linear address to be used.

6. The computer product of claim 1, wherein a portion of the linear address is used to index into the located translation table to locate a translation table entry, the translation table entry comprising an origin address of a next level translation table of the hierarchy of translation tables.

7. The computer program product of claim 1, wherein the linear address includes a page identifier and a byte offset identifier.

8-14. -14. (canceled)

15. A computer system for accessing a memory location, the system comprising:

a memory; and

a processor configured to perform a method comprising;

receiving a request to access a desired block of memory, the request comprising an effective address that includes an effective segment identifier (ESID) and a linear address, the linear address comprising a most significant portion and a byte index;

locating, by a processor, an entry, in a buffer, the entry including the ESID of the effective address; and

based on the entry including a radix page table pointer (RPTP), performing;

using the RPTP to locate a translation table of a hierarchy of translation tables;

using the located translation table to translate the most significant portion of the linear address to obtain an address of a block of memory; and

based on the obtained address, performing the requested access to the desired block of memory.

16. The system of claim 15, wherein based on the entry including a VSID, performing locating a page table entry of a group of translation table entries using a hash function to obtain an address of a block of memory.

17. The system of claim 15, wherein the using the obtained address comprises using the byte index of the linear address and the obtained address to form an address of the desired block of memory.

18. The system of claim 15, wherein the table level of the located translation table of the hierarchy of translation tables is indicated by the RPTP.

19. The system of claim 15, wherein the RPTP specifies size of the linear address to be used.

20. The system of claim 15, wherein a portion of the linear address is used to index into the located translation table to locate a translation table entry, the translation table entry comprising an origin address of a next level translation table of the hierarchy of translation tables.