Vertical Memory Device and Method for Making Thereof
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Abstract
Described herein is a method for forming a vertical memory device (150) having a vertical channel region (113) sandwiched between a source region (109, 112) and a drain region (114). A charge trapping layer (106) is provided either side of the vertical channel region (113) and associated source and drain regions (109, 112, 114). The source region (109, 112) comprises a junction between a first region (109) comprising a first doping type with a first doping concentration and a second region (112) comprising a second doping type which is opposite to the first doping type and with a second doping concentration. The drain region (114) comprises the first doping type with a first doping concentration. In another embodiment, the drain region has two regions of differing doping types and concentrations and the source region comprises the first doping type with the first doping concentration.
34 Citations
35 Claims
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1-15. -15. (canceled)
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16. A method comprising:
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providing a semiconductor substrate; providing (i) a first top layer on the semiconductor substrate and (ii) a second top layer on the first top layer, thereby forming a semiconducting substrate comprising the semiconductor substrate, the first top layer, and the second top layer, wherein the first top layer comprises a first type of dopants and the second top layer comprises a second type of dopants different from the first type of dopants; providing a stack of layers on the semiconducting substrate, wherein the stack of layers comprises at least a first dielectric layer, a conductive layer formed on the first dielectric layer, and a second dielectric layer formed on the conductive layer; providing a hole in the stack of layers, thereby exposing a portion of the semiconducting substrate; providing a gate dielectric at least at sidewall surfaces of the hole; providing a substantially undoped semiconducting material in the hole, thereby forming a middle region of the hole; providing a doped semiconducting material on the stack and on the substantially undoped semiconducting material in the hole, wherein the doped semiconducting material comprises the first type of dopants; using a first anneal to form a bottom region of the hole, wherein the bottom region comprises (i) a first bottom region adjacent to the second top layer and comprising the first type of dopants and (ii) a second bottom region adjacent to the first bottom region and the middle region and comprising the second type of dopants; and using a second anneal to form a top region of the hole, wherein the top region is adjacent to the middle region and comprises dopants of the first doping type. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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23. A method comprising:
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providing a semiconductor substrate; providing a top layer on the semiconductor substrate, thereby forming a semiconducting substrate comprising the semiconductor substrate and the top layer, wherein the top layer comprises a first type of dopants; providing a stack of layers on the semiconducting substrate, wherein the stack of layers comprises at least a first dielectric layer, a conductive layer formed on the first dielectric layer, and a second dielectric layer formed on the conductive layer; providing a hole in the stack of layers, thereby exposing a portion of the semiconducting substrate; providing a gate dielectric at least at sidewall surfaces of the hole; providing a substantially undoped semiconducting material in the hole, thereby forming a middle region of the hole; using an anneal to form a bottom region of the hole, wherein the bottom region is adjacent to the top layer and the middle region and comprises dopants of the first doping type; providing a first doped semiconducting material on the substantially undoped semiconducting material in the hole, thereby forming a first top region of the hole, wherein the first doped semiconducting material comprises a second type of dopants different from the first type of dopants; and providing a second doped semiconducting material over the first doped semiconducting material, thereby forming a second top region of the hole, wherein the second doped semiconducting material comprises the first type of dopants. - View Dependent Claims (24, 25, 26, 27, 28)
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29. A vertical memory device comprising:
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a semiconducting substrate; a vertical semiconducting region formed on the semiconducting substrate, wherein the vertical semiconducting region comprises a source region, a drain region, and a channel region positioned between the source region and the drain region; a horizontal stack formed adjacent to the vertical semiconducting region, wherein the horizontal gate stack comprises a first dielectric layer, a second dielectric layer, and a conductive gate layer positioned between the first dielectric layer and the second dielectric layer; and a charge-trapping layer formed at least between the vertical semiconducting region and the conductive gate layer, wherein at least one of the source region and the drain region comprises (i) a first region adjacent to the channel region and comprising a first type of dopants and (ii) a second region adjacent to the first region and comprising a second type of dopants different than the first type of dopants. - View Dependent Claims (30, 31, 32, 33, 34, 35)
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Specification