PACKAGING TO REDUCE STRESS ON MICROELECTROMECHANICAL SYSTEMS

• US 20130341737A1
• Filed: 09/18/2011
• Published: 12/26/2013
• Est. Priority Date: 09/18/2010
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Bryzek, Janusz, Bloomsburgh, John Gardner, Acar, Cenk
• Granted Patent: US 9,156,673 B2
• Time in Patent Office: Days
• US Class Current: 257/415
• CPC Class Codes: B81B 3/0021 Transducers for transforming electrical into mechanical energy or vice versa dynamo-electric machines H02K99/00; electrostatic machines H02N1/00; piezoelectric devices H10N30/00
• CPC Class Codes: B81B 3/0072 For controlling internal stress or strain in moving or flexible elements, e.g. stress compensating layers
• CPC Class Codes: B81B 7/0016 Protection against shocks or vibrations, e.g. vibration damping
• CPC Class Codes: B81B 7/0051 between the package lid and the substrate
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: B81C 2203/0785 Transfer and j oin technology, i.e. forming the electronic processing unit and the micromechanical structure on separate substrates and joining the substrates
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 29/84 controllable by variation of applied mechanical force, e.g. of pressure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

One example includes an integrated circuit including at least one electrical interconnects disposed on an elongate are extending away from a main portion of the integrated circuit and a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the integrated circuit.

Claims

1. An apparatus, comprising:

an integrated circuit including at least one electrical interconnect disposed on an elongate arm extending away from a main portion of the integrated circuit , with a gap between the main portion and one side the elongate arm; and

a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the integrated circuit.

2. The apparatus of claim 1, wherein the microelectromechanical layer is bumped onto the integrated circuit.

3. The apparatus of claim 1, wherein the microelectromechanical layer includes at least one electrical interconnect disposed on a microelectromechanical layer elongate arm extending away from a main portion of the microelectromechanical layer.

4. The apparatus of claim 3, wherein the microelectromechanical layer includes a via layer that includes the microelectromechanical layer elongate arm, with a slideable microelectromechanical proof-mass coupled to the via.

5. The apparatus of claim 1, comprising a cluster of electrical interconnects disposed on the integrated circuit to couple the integrated circuit to a substrate.

6. The apparatus of claim 5, wherein the cluster is centrally disposed on the integrated circuit.

7. The apparatus of claim 5, wherein the cluster is disposed at a corner of the integrated circuit.

8. The apparatus of claim 1, comprising a cluster of electrical interconnects centrally disposed on the microelectromechanical layer to couple the microelectromechanical layer to the integrated circuit.

9. The apparatus of claim 1, wherein the elongate arm is etched and the at least one electrical interconnect includes polymer-core copper.

10. The apparatus of claim 1, wherein the elongate arm is part of a plurality of elongate arms, wherein for each respective elongate arm on a side of the integrated circuit, there is an opposing elongate are on an opposite side of the integrated circuit.

11. A method, comprising:

forming an integrated circuit;

forming the integrated circuit to define a plurality of elongate arms that extend away from a main portion of the integrated circuit to which the microelectromechanical layer is coupled;

stacking the integrated circuit onto a substrate and electrically and physically coupling the integrated circuit to the substrate using a plurality of electrical interconnects, wherein electrically and physically coupling the integrated circuit to the substrate using a plurality of electrical interconnects includes electrically and physically coupling the integrated circuit to the substrate using the plurality of elongate arms;

stacking a microelectromechanical layer onto the integrated circuit and electrically and physically coupling the microelectromechanical layer to the integrated circuit such that the microelectromechanical layer is electrically coupled to the substrate via a circuit of the integrated circuit.

12. The method of claim 11, comprising excising a void in the substrate and disposing the microelectromechanical layer at least partially in the void.

13. The method of claim 11, comprising disposing a seal between the microelectromechanical layer and the integrated circuit to define a hermetically sealed void between the microelectromechanical layer and the integrated circuit.

14. The method of claim 13, wherein disposing a seal comprising soldering a solder ring.

15. The method of claim 13, wherein disposing a seal includes disposing underfill.