TEST INTERFACE BOARDS AND TEST SYSTEMS

• US 20130342236A1
• Filed: 03/14/2013
• Published: 12/26/2013
• Est. Priority Date: 06/26/2012
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, Ki-Jae, Yoo, Jong-Woon, Han, Sang-Kyeong, Kim, Gil-Beag
• Application Number:
  US13/804,149
• Publication Number:
  US 20130342236A1
• Time in Patent Office: Days
• US Class Current: 324/756.07
• CPC Class Codes: G01R 1/0408 Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets G01R1/067 takes precedence; mass production testing systems G01R31/59; testing of connections G01R31/66; for testing printed circuit boards G01R31/2808
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Abstract

A test interface board comprises at least one switch matrix including a plurality of switching elements that connect a plurality of connection nodes to each other. The at least one switch matrix is configured to connect a plurality of channels of an automatic test equipment (ATE) to respective pin positions corresponding to a device under test (DUT) in response to switching control signals. The plurality of channels provide test operation signals for testing the DUT. A control logic is configured to generate the switching control signals based on pin configuration information of the DUT.

Claims

1. A test interface board comprising:

at least one switch matrix including a plurality of switching elements that connect a plurality of connection nodes to each other, the at least one switch matrix configured to connect a plurality of channels of an automatic test equipment (ATE) to respective pin positions corresponding to a device under test (DUT) in response to switching control signals, the plurality of channels providing test operation signals for testing the DUT; and

a control logic configured to generate the switching control signals based on pin configuration information of the DUT.

2. The test interface board of claim 1, wherein each of the plurality of connection nodes is formed at intersection point of each of a plurality of first paths arranged to extend in a first direction and a plurality of second paths arranged to extend in a second direction transverse to the first direction.

3. The test interface board of claim 1, wherein the plurality of switching elements comprises:

a plurality of row switching elements configured to selectively connect two adjacent connection nodes of the plurality of connection nodes arranged to extend in a first direction in response to the switching control signals; and

a plurality of column switching elements configured to selectively connect two adjacent connection nodes of the plurality of connection nodes arranged to extend in a second direction that is transverse the first direction in response to the switching control signals.

4. The test interface board of claim 1, wherein the at least one switch matrix comprises first and second switch matrices which are positioned on respective first and second layers, and

wherein the test interface board further comprises a plurality of interlayer switching elements configured to selectively connect first connection nodes in the first switch matrix on the first layer to corresponding second connection nodes in the second switch matrix on the second layer.

5. The test interface board of claim 4, wherein the plurality of interlayer switching elements are configured to provide non-overlapping test signal paths when connections between the plurality of channels and the corresponding pin positions overlap in a same switch matrix.

6. The test interface board of claim 4, wherein the plurality of interlayer switching elements comprise a plurality of transistors that are turned-on/off in response to the switching control signals.

7. The test interface board of claim 4, wherein the plurality of interlayer switching elements comprise a plurality of two-terminal switches that are connected/disconnected in response to the switching control signals.

8. The test interface board of claim 1, wherein the switching elements comprise a plurality of transistors that are turned-on/off in response to the switching control signals.

9. The test interface board of claim 1, wherein the switching elements comprise a plurality of two-terminal switches that are connected/disconnected in response to the switching control signals.

10. The test interface board of claim 1, wherein the at least one switch matrix comprises:

a first switching unit including first switching elements that switch a control signal and a test pattern signal of the test operation signals in response to first switching control signals; and

a second switching unit including second switching elements that switch one of output of the first switching unit, a power supply voltage and a ground voltage to provide the switched one to the pin positions in response to second switching control signals.

11. The test interface board of claim 1, wherein the control logic comprises:

a register that stores the pin configuration information; and

a switching signal generator configured to generate the switching control signals based on the pin configuration information stored in the register.

12. The test interface board of claim 11, wherein the register comprises a mode set register that stores the pin configuration information.

13. The test interface board of claim 1, wherein when the DUT is changed, the at least one switch matrix provides reconfigurable test signal paths connecting the channels to the corresponding pin positions of the changed DUT in response to the switching control signals.

14. A test system comprising:

an automatic test equipment (ATE) configured to generate test operation signals;

a device under test (DUT) that receives the test operation signals to output test result signals in response to test pattern signals of the test operation signals; and

a test interface board configured to transfer the test operation signals to the DUT, wherein the test interface board comprises;

at least one switch matrix including a plurality of switching elements that connect a plurality of connection nodes to each other, the at least one switch matrix configured to connect a plurality of channels of the ATE to respective pin positions corresponding to the DUT in response to switching control signals, the plurality of channels providing test operation signals for testing the DUT; and

a control logic configured to generate the switching control signals based on pin configuration information of the DUT.

15. The test system of claim 14, wherein the plurality of switching elements comprises:

a plurality of row switching elements configured to selectively connect two adjacent connection nodes of the plurality of connection nodes arranged to extend in a first direction in response to the switching control signals; and

a plurality of column switching elements configured to selectively connect two adjacent connection nodes of the plurality of connection nodes arranged to extend in a second direction that is transverse the first direction in response to the switching control signals.

16. The test system of claim 14,

wherein the at least one switch matrix comprises first and second switch matrices which are positioned on respective first and second layers,

wherein the test interface board further comprises a plurality of interlayer switching elements configured to selectively connect first connection nodes in the first switch matrix on the first layer to corresponding second connection nodes in the second switch matrix on the second layer, and

wherein the plurality of interlayer switching elements are configured to provide non-overlapping test signal paths when connections between the plurality of channels and the corresponding pin positions overlap in a same switch matrix.

17. A test interface board, comprising:

a plurality of nodes arranged in a matrix having a first direction of extension and a second direction of extension, the first and second directions being transverse each other;

a plurality of first switching elements configured to selectively connect adjacent nodes arranged in the first direction in response to switching control signals;

a plurality of second switching elements configured to selectively connect adjacent nodes arranged in the second direction in response to the switching control signals; and

a plurality of first positions corresponding to channels of an automated test equipment (ATE) and a plurality of second positions corresponding to pin positions of a device under test (DUT), wherein, in response to the switching control signals, the test interface board is programmed to provide multiple test signal paths, a signal path being between a selected one of the plurality of first positions and a selected one of the plurality of second positions, and the signal path further including a selected plurality of the nodes selectively connected by the first and second switching elements.

18. The test interface board of claim 17, wherein the nodes and first and second switching elements are arranged on first and second layers, each of the first and second layers comprising a plurality of nodes, a plurality of first switching elements and a plurality of second switching elements, and further comprising a plurality of third switching elements configured to selectively connect adjacent nodes of the first and second layers.

19. The test interface board of claim 18, wherein the signal path further includes selected nodes of the first and second layers selectively connected by the third switching elements.

20. The test interface board of claim 18, wherein two signal paths that otherwise would intersect on one of the first and second layers, are configured to overlap through the third switching elements and nodes of the other of the first and second layers.