SIGE BASED GATE DRIVEN PMOS TRIGGER CIRCUIT

• US 20130342941A1
• Filed: 06/26/2012
• Published: 12/26/2013
• Est. Priority Date: 06/26/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Wen-Han, Chen, Kuo-Ji
• Granted Patent: US 9,184,586 B2
• Time in Patent Office: Days
• US Class Current: 361/56
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

Some embodiments of the present disclosure relate to a low-power, area efficient ESD protection device that provides ESD protection to an ESD susceptible circuit. The ESD protection device has a trigger circuit with a resistor. The resistor has a first terminal connected to the first external pin and a second terminal connected directly to a gate of a SiGe based PMOS shunt transistor. The trigger circuit generates a trigger signal that drives the gate of the PMOS device to shunt power away from the ESD susceptible circuit when an ESD event is present. The SiGe based PMOS shunt transistor has a lower gate leakage than a conventional NMOS shunt transistors, thereby providing for an ESD circuit with a low leakage current at small gate lengths.

Claims

1. An integrated chip, comprising:

an electrostatic discharge (ESD) susceptible circuit electrically connected to a first circuit node having a first voltage and a second circuit node having a second voltage; and

an ESD protection device, configured to act as an interface between the ESD susceptible circuit and external integrated chip pins, comprising;

a trigger circuit configured to generate a trigger signal, having a value dependent upon an ESD event, at a trigger circuit output node;

a voltage controlled shunt network comprising a silicon germanium (SiGe) PMOS shunt transistor with a source connected to the first circuit node, a drain connected to the second circuit node, and a gate connected directly to the trigger circuit output node and configured to receive a voltage value that is substantially equal to a voltage value of the trigger signal.

2. The integrated chip of claim 1, wherein the trigger circuit comprises:

a resistive element having a first terminal connected to the first circuit node and a second terminal connected to the trigger circuit output node; and

a capacitive element coupled to the resistive element and having a first terminal connected to the trigger circuit output node and a second terminal connected to the second circuit node.

3. The integrated chip of claim 2, wherein the capacitive element comprises a gate capacitance of the SiGe PMOS shunt transistor.

4. The integrated chip of claim 2, wherein the capacitive element comprises a MOS capacitor having a source and drain connected to the drain of the SiGe PMOS shunt transistor, a gate connected to the resistive element, and a body connected to a third circuit node comprising a ground terminal.

5. The integrated chip of claim 2, further comprising:

a timing delay circuit having an input node connected to the trigger circuit output node, wherein the timing delay circuit is configured to selectively connect the trigger circuit output node to a ground terminal when the ESD event is present so as to extend a turn-on-time of the SiGe PMOS shunt transistor.

6. The integrated chip of claim 5, wherein the timing delay circuit comprises:

an inverter having a first inverting element and a second inverting element arranged in series between the first circuit node and the second circuit node, wherein an input node of the inverter is connected to the trigger circuit output node; and

an NMOS transistor having a gate connected to an output terminal of the inverter, a drain connected to the trigger circuit output node, and a source connected to the second circuit node.

7. The integrated chip of claim 6, wherein

the first inverting element comprises a PMOS transistor having a source to body connection;

and

the second inverting element comprises an NMOS transistor having a source to body connection.

8. The integrated chip of claim 2, wherein the SiGe PMOS shunt transistor comprises:

a source region comprising a first, p-type SiGe region within an n-type substrate;

a drain region comprising a second, p-type SiGe region within the n-type substrate;

a channel region extending between the first and second p-type SiGe regions;

a gate electrode located over the channel region, and separated from the channel region by a gate oxide; and

a first metal interconnect layer configured to connect the gate electrode to a polysilicon resistor or an oxide definition resistor that comprises the resistive element.

9. The integrated chip of claim 1, wherein the SiGe PMOS shunt transistor comprises a source to body connection.

10. An electrostatic discharge (ESD) protection device to protect a circuit, which is electrically connected to first and second circuit nodes, from an ESD event, the ESD protection device comprising:

a first electrical path extending between first and second circuit nodes and having a trigger circuit comprising a resistive element and a capacitive element connected to one another at a trigger circuit output node; and

a second electrical path extending between the first and second circuit nodes and comprising a silicon germanium (SiGe) PMOS shunt transistor with a source connected to the first circuit node, a drain connected to the second circuit node, and a gate connected directly to the trigger circuit output node.

11. The ESD protection device of claim 10, wherein the capacitive element comprises a gate capacitance of the SiGe PMOS shunt transistor, such that a section of the first electrical path is coincident with a section of the second electrical path.

12. The ESD protection device of claim 10,

wherein the first electrical path is in parallel with the second electrical path;

and

wherein the capacitive element comprises a MOS capacitor having a source and drain connected to the drain of the SiGe PMOS shunt transistor, a gate connected to the resistive element, and a body connected to a third circuit node comprising a ground terminal.

13. The ESD protection device of claim 10, further comprising:

a timing delay circuit having an input node connected to the trigger circuit output node, wherein the timing delay circuit is configured to selectively connect the trigger circuit output node to a ground terminal when the ESD event is present so as to extend a turn-on-time of the SiGe PMOS shunt transistor.

14. The ESD protection device of claim 13, wherein the timing delay circuit comprises:

an inverter having a first inverting element and a second inverting element arranged in series between the first circuit node and the second circuit node, wherein the inverter is configured to receive a trigger signal from the trigger circuit; and

an NMOS transistor having a gate connected to an output terminal of the inverter, a drain connected to the trigger circuit output node, and a source connected to the second circuit node.

15. The ESD protection device of claim 10, wherein the SiGe PMOS shunt transistor comprises:

a source region comprising a first, p-type SiGe region within an n-type substrate;

a drain region comprising a second, p-type SiGe region within the n-type substrate;

a channel region extending between the first and second p-type SiGe regions;

a gate electrode located over the channel region, and separated from the channel region by a gate oxide; and

a first metal interconnect layer configured to connect the gate electrode to a polysilicon resistor comprising the resistive element.

16. A method of forming an ESD protection device, comprising:

providing an electrostatic discharge (ESD) susceptible circuit electrically connected to a first circuit node having a first voltage and a second circuit node having a second voltage;

providing a trigger circuit comprising a resistive element having a first terminal connected to the first circuit node and a second terminal connected to a trigger circuit output node; and

directly connecting a gate of a SiGe PMOS shunt transistor to the trigger circuit output node so that the gate of the SiGe PMOS shunt transistor receives a voltage value that is substantially equal to a voltage value at the trigger circuit output node.

17. The method of claim 16, wherein the SiGe PMOS shunt transistor comprises a source to body connection.

18. The method of claim 16, wherein the trigger circuit further comprises a capacitive element connected between the trigger circuit output node and the second circuit node.

19. The method of claim 18, wherein the capacitive element comprises a gate capacitance of the SiGe PMOS shunt transistor.

20. The method of claim 16, further comprising:

connecting the trigger circuit output node to timing delay circuit configured to selectively connect the trigger circuit output node to a ground terminal when an ESD event is present so as to extend a turn-on-time of the SiGe PMOS shunt transistor.