FLASHMEMORY PROGRAM INHIBIT SCHEME

• US 20130343123A2
• Filed: 10/16/2012
• Published: 12/26/2013
• Est. Priority Date: 11/30/2006
• Status: Abandoned Application

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: KIM, Jin-Ki
• Application Number:
  US13/652,947
• Publication Number:
  US 20130039125A1
• Time in Patent Office: Days
• US Class Current: 365/185.02
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a NAND string where no programming is desired, is decoupled from the other cells in the NAND string. This allows the channel of the decoupled cell to be locally boosted to a voltage level sufficient for inhibiting F-N tunneling when the corresponding wordline is raised to a programming voltage. Due to the high boosting efficiency, the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming.

Claims

1. An apparatus for minimizing program disturb in NAND string having a selected memory cell, upper memory cells between the selected memory cell and a bitline, lower memory cells between the selected memory cell and a sourceline, and a string select transistor for coupling the memory cells to the bitline, the apparatus comprising:

a voltage source for providing a voltage level corresponding to program inhibit voltage from the bitline to the NAND string;

a precharge source for precharging channels of the selected memory cell and the upper memory cells to a primary boosted voltage level after the voltage level is coupled to the channel of the NAND string by driving a selected wordline connected to the selected memory cell and upper wordlines connected to the upper memory cells to a first pass voltage level, and driving lower wordlines connected to the lower memory cells to a second pass voltage, the second pass voltage being less than the first pass voltage; and

a memory cell booster for locally boosting the selected memory cell channel to a secondary boosted voltage level after the channel is precharged, the secondary boosted voltage level being higher than the primary boosted voltage level by driving the selected wordline connected to the selected memory cell to a programming voltage level, and electrically turning off an upper memory cell adjacent to the selected memory cell.