METHOD OF FABRICATING NMOS DEVICES

• US 20130344697A1
• Filed: 12/28/2012
• Published: 12/26/2013
• Est. Priority Date: 06/21/2012
• Status: Abandoned Application

• Current Assignee: Shanghai Huali Microelectronics Corporation
• Original Assignee: Shanghai Huali Microelectronics Corporation
• Inventors: XU, Qiang
• Application Number:
  US13/730,446
• Publication Number:
  US 20130344697A1
• Time in Patent Office: Days
• US Class Current: 438/694
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions

Abstract

A method of fabricating n-channel metal-oxide-semiconductor (NMOS) devices is disclosed, the method including: providing a substrate having a plurality of NMOS structures formed thereon; depositing a silicon nitride layer having a high tensile stress over the substrate; and sequentially exposing and dry etching a plurality of portions of the silicon nitride layer in an order of channel lengths of the plurality of NMOS structures such that each portion of the etched silicon nitride layer has a thickness proportional to the channel length of its corresponding NMOS structure. Compared to a conventional method, the above fabrication method of NMOS devices can achieve uniform performance adjustment of NMOS devices after a silicon nitride layer with a high tensile stress is deposited.

Claims

1. A method of fabricating n-channel metal-oxide-semiconductor (NMOS) devices, the method comprising the steps of:

providing a substrate having a plurality of NMOS structures formed thereon;

depositing a silicon nitride layer having a high tensile stress over the substrate; and

sequentially exposing and dry etching a plurality of portions of the silicon nitride layer in an order of channel lengths of the plurality of NMOS structures such that each portion of the etched silicon nitride layer has a thickness proportional to the channel length of its corresponding NMOS structure.

2. The method according to claim 1, wherein the silicon nitride layer is deposited by a plasma enhanced chemical vapor deposition method.

3. The method according to claim 1, wherein the silicon nitride layer has a thickness of 300 Å

to 800 Å

.

4. The method according to claim 1, wherein the silicon nitride layer has a stress of 0.7 GPa to 2.0 GPa.

5. The method according to claim 1, wherein the order of channel lengths of the plurality of NMOS structures is an order from a shortest channel length to a longest channel length, or an order from a longest channel length to a shortest channel length.

6. The method according to claim 1, wherein the plurality of portions of the silicon nitride layer are dry etched by using an etchant gas with low fluorine and carbon contents.

7. The method according to claim 6, wherein the etchant gas is any one, or a combination of more than one, selected from the group consisting of carbon tetrafluoride, octafluorocyclobutane and perfluorinated butadiene.

8. The method according to claim 1, further comprising a step of depositing a pre-metal dielectric layer.