WEAR LEVELING MEMORY USING ERROR RATE

• US 20130346812A1
• Filed: 06/22/2012
• Published: 12/26/2013
• Est. Priority Date: 06/22/2012
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bahirat, Shirish D., Marquart, Todd A.
• Application Number:
  US13/531,139
• Publication Number:
  US 20130346812A1
• Time in Patent Office: Days
• US Class Current: 714/704
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

The present disclosure relates to wear leveling memory using error rate. A number of embodiments comprise: programming data to a selected group of a number of groups of memory cells based, at least partially, on a process cycle count corresponding to the selected group; determining an error rate corresponding to the selected group; and adjusting the process cycle count corresponding to the selected group based, at least partially, on the determined error rate corresponding to the selected group.

Claims

1. A method for operating a memory, comprising:

programming data to a selected group of a number of groups of memory cells based, at least partially, on a process cycle count corresponding to the selected group;

determining an error rate corresponding to the selected group; and

adjusting the process cycle count corresponding to the selected group based, at least partially, on the determined error rate corresponding to the selected group.

2. The method of claim 1, including determining the error rate corresponding to the selected group responsive to the process cycle count corresponding to the selected group reaching or exceeding one of a number of threshold process cycle counts.

3. The method of claim 1, wherein the method includes determining the error rate corresponding to the selected group only if the process cycle count corresponding to the selected group has reached or exceeded a threshold process cycle count.

4. The method of claim 1, wherein the method includes maintaining a process cycle count for each respective group of the number of groups of memory cells.

5. The method of claim 1, including determining the error rate using an error detection/correction component coupled to the memory.

6. The method of claim 1, wherein the process cycle count is a program/erase cycle count.

7. The method of claim 1, determining an error rate corresponding to the selected group comprises performing a background sampling of error rates corresponding to the respective number of groups of memory cells.

8. A method for operating a memory, comprising:

determining a number of error rates each corresponding to a respective one of a number of groups of memory cells; and

adjusting a maintained process cycle count corresponding to at least one of the number of groups of memory cells responsive to the determined number of error rates.

9. The method of claim 8, including determining the number of error rates each corresponding to a respective one of the number of groups of memory cells responsive to a threshold process cycle count of a number of threshold process cycle counts having been reached or exceeded.

10. The method of claim 8, including adjusting the maintained process cycle count corresponding to the at least one of the number of groups of memory cells responsive only to a threshold process cycle count of a number of threshold process cycle counts having been reached or exceeded.

11. The method of claim 8, including:

maintaining process cycle counts corresponding to each of the respective groups of memory cells;

determining which of the respective groups of memory cells is to receive data in association with a program operation based on the maintained process cycle counts until a threshold process cycle count is reached or exceeded; and

determining which of the respective groups of memory cells is to receive data in association with a program operation based on determined error rates corresponding to the respective groups of memory cells subsequent to the threshold process cycle count being reached or exceeded.

12. The method of claim 8, wherein determining the number of error rates each corresponding to a respective one of a number of groups of memory cells includes determining the number of error rates only at particular threshold process cycle counts.

13. A method for operating a memory, comprising:

performing wear leveling on the memory based on a number of process cycle counts each corresponding to a respective one of a number of groups of memory cells;

determining a number of error rates each corresponding to a respective one of the number of groups of memory cells;

adjusting the number of process cycle counts corresponding to the respective groups based, at least partially, on the determined error rates corresponding to the respective groups.

14. The method of claim 13, including determining the number of error rates by using a controller configured to control determining the number of error rates via a background sampling method.

15. The method of claim 13, wherein performing wear leveling includes selecting a particular group of the number of groups of memory cells to receive data in association with a programming operation, the particular group being a group having a lowermost process cycle count corresponding thereto.

16. The method of claim 13, wherein adjusting the number of process cycle counts includes adjusting at least one of the number of process cycle counts from an actual amount of process cycles performed on a respective one of the number of groups to an amount of process cycles other than the actual amount of process cycles.

17. The method of claim 16, wherein adjusting the at least one of the number of process cycle counts from the actual amount of process cycles performed on the respective one of the number of groups to the amount of process cycles other than the actual amount of process cycles includes decreasing the at least one of the number of process cycle counts responsive to the determined error rate corresponding to the respective one of the number of groups.

18. The method of claim 16, wherein adjusting the at least one of the number of process cycle counts from the actual amount of process cycles performed on the respective one of the number of groups to the amount of process cycles other than the actual amount of process cycles includes increasing the at least one of the number of process cycle counts responsive to the determined error rate corresponding to the respective one of the number of groups.

19. An apparatus, comprising:

a memory comprising a number of groups of memory cells; and

a controller coupled to the memory and configured to control;

performing wear leveling on the memory based on a number of process cycle counts each corresponding to a respective one of the number of groups of memory cells; and

adjusting the process cycle count corresponding to a selected group of the number of groups based, at least partially, on a determined error rate corresponding to the selected group.

20. The apparatus of claim 19, wherein the number of groups of memory cells are a number of blocks of memory cells configured to be erased together in association with an erase operation.

21. The apparatus of claim 19, wherein the number of groups of memory cells are a number of pages of memory cells configured to be programmed together in association with a programming operation.

22. The apparatus of claim 19, wherein the controller is configured to control:

maintaining process cycle counts corresponding to each of the respective groups of memory cells;

determining which of the respective groups of memory cells is to receive data in association with a program operation based on the maintained process cycle counts until a threshold process cycle count is reached or exceeded; and

determining which of the respective groups of memory cells is to receive data in association with a program operation based on determined error rates corresponding to the respective groups of memory cells subsequent to the threshold process cycle count being reached or exceeded.

23. The apparatus of claim 19, wherein the controller is configured to control determining error rates corresponding to the respective number of groups via a sampling method that is performed while data is being programmed to the memory in association with a program operation and/or while data is being read from the memory in association with a read operation.

24. An apparatus, comprising:

a memory comprising a number of groups of memory cells; and

a controller coupled to the memory and configured to control;

determining that a process cycle count corresponding to a respective one of the number of groups has reached or exceeded a threshold process cycle count;

determining an error rate corresponding to the respective one of the number of groups; and

retiring the respective one of the number of groups of memory cells responsive to the determined error rate reaching or exceeding a threshold error rate.

25. The apparatus of claim 24, wherein the controller is configured to control:

tracking a total amount of data programmed to the memory; and

performing wear leveling on the memory based on error rates corresponding to the respective number of groups only if the total amount of data programmed to the memory reaches or exceeds a threshold total amount of data.

26. The apparatus of claim 25, wherein the controller is configured to control:

performing wear leveling on the memory based on process cycle counts corresponding to the respective number of groups until the total amount of data programmed to the memory reaches or exceeds the threshold total amount of data.

27. The apparatus of claim 26, wherein the threshold total amount of data corresponds to a lifetime specification of the memory.

28. The apparatus of claim 24, wherein the process cycle count corresponds to an amount of program/erase (P/E) cycles performed on the respective one of the number of groups of memory cells.

29. The apparatus of claim 24, wherein the controller is configured to control determining the error rate corresponding to the respective one of the number of groups responsive to the respective one of the number of groups reaching or exceeding the threshold process cycle count.

30. A method for operating a memory, comprising:

selecting a group of memory cells to program based on process cycle counts if a threshold amount of total data programmed to the memory has not been reached or exceeded; and

if the threshold amount of total data programmed to the memory has bee reached or exceeded, selecting a group of memory cells to be programmed based on error rates.

31. A method for operating a memory, comprising:

basing wear leveling on process cycle counts until a threshold process cycle count is reached or exceeded; and

basing wear leveling on error rates after the threshold process cycle count is reached or exceeded.

32. A method for operating a memory, comprising:

determining that a process cycle count corresponding to a respective one of a number of groups of memory cells has reached or exceeded a threshold process cycle count;

determining an error rate corresponding to the respective one of the number of groups; and

retiring the respective one of the number of groups of memory cells responsive to the determined error rate reaching or exceeding a threshold error rate.