MANUFACTURING METHOD OF ARRAY SUBSTRATE, ARRAY SUBSTRATE AND LCD DEVICE

• US 20140001475A1
• Filed: 07/12/2012
• Published: 01/02/2014
• Est. Priority Date: 07/02/2012
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Wang, Jun
• Granted Patent: US 8,900,938 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

A manufacturing method of the array substrate includes the steps: A. A first mask manufacturing process is adopted to from scan lines and thin film transistor (TFT) gates on a surface of a substrate. B. A second mask manufacturing process is adopted to form scan lines and data lines of the array substrate, a source electrode and a drain electrode of TFT and a conducting channel positioned between the source electrode and the drain electrode. C. A photoresistor formed in the second mask manufacturing process is incinerated, and then, an a-Si film is paved on the surface of the array substrate. D. The photoresistor is stripped to form an undoped active layer. E. A third mask manufacturing process is adopted to form a transparent conducting layer on the surface of the drain electrode of the TFT. Only three mask manufacturing process in the present disclosure are needed to manufacture the entire array substrate.

Claims

1. A manufacturing method of an array substrate, comprising the following steps:

A. adopting a first mask manufacturing process to from a scan line(s) and a thin film transistor (TFT) gate(s) on a surface of a substrate;

B. successively paving an insulating layer, a second metal layer and an n+a-Si film are on the substrate;

then, adopting a second mask manufacturing process to form a scan line(s) and a data line(s) of the array substrate, a source electrode and a drain electrode of the thin film transistor (TFT), and a conducting channel positioned between the source electrode and the drain electrode;

C. incinerating a photoresistor formed in the second mask manufacturing process to expose the n+a-Si film on both ends of the conducting channel;

then, paving an a-Si film on a surface of the array substrate and forming reliably electric connection between the formed a-Si film and the n+a-Si film on both ends of the conducting channel;

D. stripping the photoresistor and also removing the a-Si material covering the surface of the photoresistor;

forming an undoped active layer by the remaining a-Si film forms;

E. adopting a third mask manufacturing process, and reserving the n+a-Si film on the covering part of the undoped active layer to form a doped active layer;

then, forming a transparent conducting layer on the surface of the drain electrode of the thin film transistor (TFT).

2. The manufacturing method of the array substrate of claim 1, wherein in the step E, a mask manufacturing process is used to form a transparent conducting layer synchronously on the surfaces of the source electrode and the drain electrode of the TFT.

3. The manufacturing method of the array substrate of claim 1, wherein in the step E, the undoped active layer is used as a mask body, and the n+a-Si film outside the covering part of the undoped active layer is etched off to form a doped active layer;

then, the third mask manufacturing process is used to form a transparent conducting layer on the TFT surface.

4. The manufacturing method of the array substrate of claim 3, wherein in the step E, a mask manufacturing process is used to form a transparent conducting layer synchronously on the surfaces of the source electrode and the drain electrode of the TFT.

5. The manufacturing method of the array substrate of claim 1, wherein in the step E, firstly, a mask manufacturing process is adopted to form a pattern of a transparent conducting layer on the surface of the array substrate;

then, the n+a-Si material outside the covering part of the undoped active layer is removed in an etching mode through exposure and development;

the reserved n+a-Si material forms a doped active layer;

then, a layer of transparent conducting colloid is paved, and the remaining photoresist and the conducting colloid covering the surface are stripped to form the transparent conducting layer.

6. The manufacturing method of the array substrate of claim 5, wherein in the step E, a mask manufacturing process is used to form a transparent conducting layer synchronously on the surfaces of the source electrode and the drain electrode of the TFT.

7. The manufacturing method of the array substrate of claim 1, wherein the step A comprises the following steps:

A1. depositing a first metal layer on the substrate;

A2. coating a first layer of photoresist on the first metal layer;

then, making patterns of the scan lines and the TFT gates of the array substrate through exposure and development, to form the first layer of photoresistor;

A3. etching the first metal layer;

then, stripping the first layer of photoresistor to form the scan lines and the TFT gates of the array substrate;

wherein the step B comprises the following steps;

B1. successively depositing an insulating layer, a second metal layer and an n+a-Si film on the substrate;

B2. coating a second layer of photoresist on the n+a-Si film, forming a second layer of photoresistor through exposure and development, and forming a notch in the second layer of photoresistor at the region above the gates;

the notch is divided into a first square notch on the bottom and a second square notch positioned on an opening;

the width of the second square notch is larger than the width of the first square notch;

B3. using the second layer of photoresistor as a mask body for etching off the n+a-Si film material on the first square notch;

B4. After the n+a-Si film material on the first square notch is stripped, continuously etching the exposed second metal layer to form a source electrode, a drain electrode of TFT and data lines of the array substrate;

meanwhile, a conducting channel with the same width as the first square notch is also formed between the cut-off n+a-Si film and the second metal layer;

wherein the step C comprises the following steps;

C1. incinerating the second layer of photoresistor for reducing the thickness of the photoresistor, and exposing the n+a-Si film covered by both ends of the first square notch;

C2. depositing an a-Si film is deposited on the substrate, and covering the surfaces of the exposed n+a-Si film and the conducting channel by the a-Si film;

wherein the step E comprises the following steps;

E1. using the undoped active layer as a mask body, etching off the n+a-Si film material outside the covering region of the undoped active layer and forming the doped active layer by the remaining n+a Si film;

E2. adopting the third layer of photoresist;

then, forming the third layer of photoresistor on the region of the undoped active layer through exposure and development;

E3. depositing the transparent conducting layer on the substrate, and covering the surfaces of the source electrode and the drain electrode of the TFT by the transparent conducting layer;

E4. stripping the third layer of photoresistor, and also removing the transparent conducting layer on the surface of the third layer of photoresistor to form a pixel electrode of TFT.

8. The manufacturing method of the array substrate of claim 7, wherein in the step E, a mask manufacturing process is used to form a transparent conducting layer synchronously on the surfaces of the source electrode and the drain electrode of the TFT.

9. An array substrate, comprising:

a thin film transistor (TFT) structure comprising gates, an insulating layer, a metal layer and a doped active layer successively from the bottom;

wherein the region above the gates is configured with a conducting channel;

the conducting channel cuts off the doped active layer and the metal layer; and

wherein the cut-off metal layer is divided into a source electrode and a drain electrode;

the surface of the drain electrode is covered with a transparent conducting layer;

the surface of the doped active layer and the inner part of the conducting channel are covered with an undoped active layer.

10. The array substrate of claim 9, wherein the surface of the source electrode is also covered with a transparent conducting layer.

11. The array substrate of claim 10, wherein the TFT structure is axially symmetrical with respect to the central line of the conducting channel.

12. The array substrate of claim 9, wherein the doped active layer adopts an n+a-Si material;

the undoped active layer adopts an a-Si material.

13. A liquid crystal display (LCD) device, comprising:

an array substrate comprising a thin film transistor (TFT) structure;

wherein the TFT structure comprises gates, an insulating layer, a metal layer and a doped active layer successively from the bottom;

wherein the region above the gates is configured with a conducting channel;

the conducting channel cuts off the doped active layer and the metal layer; and

wherein the cut-off metal layer is divided into a source electrode and a drain electrode;

a surface of the drain electrode is covered with a transparent conducting layer;

the surface of the doped active layer and the inner part of the conducting channel are covered with an undoped active layer.

14. The LCD device of claim 13, wherein the surface of the source electrode is also covered with a transparent conducting layer.

15. The LCD device of claim 14, wherein the TFT structure is axially symmetrical with respect to the central line of the conducting channel.

16. The LCD device of claim 13, wherein the doped active layer adopts an n+a-Si material;

the undoped active layer adopts an a-Si material.