CONTACT RESISTANCE REDUCED P-MOS TRANSISTORS EMPLOYING GE-RICH CONTACT LAYER

• US 20140001520A1
• Filed: 06/29/2012
• Published: 01/02/2014
• Est. Priority Date: 06/29/2012
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Glass, Glenn A., Murthy, Anand S.
• Granted Patent: US 10,535,735 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron-doped germanium-tin alloy layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors). The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Claims

1. A transistor device, comprising:

a semiconductor body;

a gate defining a channel region within the semiconductor body;

a pair of source/drain regions on opposite sides of the channel region; and

a Ge—

Sn alloy layer on at least one of the source region/drain regions, wherein the Ge—

Sn alloy layer comprises a germanium concentration in excess of 70 atomic %, a tin concentration less than 30 atomic %, and a p-type dopant concentration in excess of 1E19 cm<sup>−

3</sup>.

2. The transistor device of claim 1, wherein the tin concentration is from 1-15 atomic %.

3. The transistor device of claim 1, wherein the tin concentration is from 3-10 atomic %.

4. The transistor device of claim 1, wherein the device is one of a planar transistor, a finFET, or a nanowire transistor.

5. The transistor device of claim 1, wherein the Ge—

Sn alloy layer is polycrystalline.

6. The transistor device of claim 1, wherein the p-type dopant is boron.

7. The transistor device of claim 1, further comprising a contact metal over the Ge—

Sn alloy layer.

8. The transistor device of claim 7, wherein the contact metal comprises a metal germanide.

9. The transistor device of claim 1, wherein the Ge—

Sn alloy layer comprises less than 10% Si.

10. The transistor device of claim 1, wherein the Ge—

Sn alloy layer comprises less than 5% Si.

11. The transistor device of claim 1, further comprising a graded buffer layer between the source/drain region and the Ge—

Sn alloy layer.

12. The transistor device of claim 11, wherein the graded buffer layer has a Ge concentration that is graded from a base level concentration compatible with the source/drain region to a high concentration in excess of 90 atomic %.

13. The transistor device of claim 11, wherein the graded buffer layer has a Sn concentration that is graded from a base level concentration compatible with the source/drain region to a high concentration less than 30 atomic %.

14. The transistor device of claim 11, wherein the graded buffer layer has a boron concentration that is graded from a base level concentration compatible with the source and drain regions to a high concentration in excess of 1E19 cm⁻

3.

15. The transistor device of claim 1, wherein the semiconductor body has a silicon concentration in excess of 10 atomic %.

16. A transistor device, comprising:

a gate defining a channel region within a silicon body;

a pair of silicon germanium source/drain regions on opposite sides of the channel region;

a Ge—

Sn alloy layer on at least one of the source region/drain regions, wherein the Ge—

Sn alloy layer comprises a germanium concentration in excess of 75 atomic %, a tin concentration less than 15 atomic %, and a boron concentration in excess of 1E19 cm<sup>−

3</sup>; and

a contact metal layer on the Ge—

Sn alloy layer.

17. The transistor device of claim 16, wherein the contact metal layer comprises a metal selected from the group consisting of Ti, Pt, Ni, and Co.

18. The transistor device of claim 17, wherein the contact metal layer further comprises a metal silicide.

19. The transistor device of claim 17, wherein the contact metal layer further comprises a metal germanide.

20. The transistor device of claim 16, further comprising a graded buffer layer between the source/drain region and the Ge—

Sn alloy layer.

21. The transistor device of claim 16, wherein the Ge—

Sn alloy layer comprises less than 5% Si.

22. A method, comprising:

forming a gate stack defining a channel region of a semiconductor device and a pair of source/drain regions on opposite sides of the channel region;

blanket depositing a dielectric material over the semiconductor device;

etching a trench in the dielectric material to expose at least a portion of at least one of the source/drain regions; and

forming a Ge—

Sn alloy layer within the trench on the source/drain region, wherein the Ge—

Sn alloy layer comprises a germanium concentration in excess of 70 atomic %, a tin concentration less than 30 atomic %, and a p-type dopant concentration in excess of 1E19 cm<sup>−

3</sup>.

23. The method of claim 22, further comprising depositing a contact metal layer over the Ge—

Sn alloy layer.

24. The method of claim 23, further comprising depositing contact plug over the contact metal layer.

25. The method of claim 22, further comprising forming a graded buffer layer over the source/drain region.

26. The method of claim 22, wherein the Ge—

Sn alloy layer is formed by selective deposition/molecular beam epitaxy.

27. The method of claim 22, wherein the Ge—

Sn alloy layer is formed by chemical vapor deposition.