THROUGH GATE FIN ISOLATION

• US 20140001572A1
• Filed: 06/29/2012
• Published: 01/02/2014
• Est. Priority Date: 06/29/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Mark T. Bohr
• Inventors: Cea, Stephen M., BOHR, Mark T., Chappell, Barbara A.
• Granted Patent: US 11,037,923 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes.

Claims

1. A microelectronic device, comprising:

a first gate electrode disposed over a first semiconductor fin;

a second gate electrode disposed over a second semiconductor fin,

a first isolation region disposed between the first and second gate electrodes and separating adjacent ends of the first and second semiconductor fins,

wherein the first electrode, second gate electrode, and first isolation region are substantially parallel with longitudinal centerlines at a substantially equal pitch.

2. The microelectronic device of claim 1, further comprising a second isolation region disposed on an end of the first semiconductor fin opposite the first isolation region, wherein centerlines of the first and second isolation regions define an isolation region pitch that is an integer multiple of a minimum pitch for the gate electrodes.

3. The microelectronic device of claim 2, wherein centerlines the first and second gate electrodes define a gate electrode pitch that is an integer multiple of the minimum gate electrode pitch.

4. The microelectronic device of claim 3, wherein the gate electrode pitch is substantially equal to the isolation region pitch with the gate electrodes and isolation regions forming stripes at a minimum stripe pitch.

5. The microelectronic device of claim 4, further comprising a third gate electrode disposed over the first semiconductor fin between the first and second isolation regions, wherein centerlines of the first and third gate electrodes are at the minimum stripe pitch and the isolation region pitch is substantially equal to at least two times the minimum stripe pitch.

6. The microelectronic device of claim 1, wherein the isolation region abuts the ends of the first and second semiconductor fins and has a transverse width that is no larger than a width of a gate stack that includes both the gate electrode and a gate dielectric layer in contact with the gate electrode.

7. The microelectronic device of claim 1, further comprising a third and fourth semiconductor fins, wherein the first gate electrode is disposed over both the first and third semiconductor fins and the second gate electrode is disposed over both the second and fourth semiconductor fins, and wherein the first isolation region separates adjacent ends of the first and second semiconductor fins and the third and fourth semiconductor fins.

8. The microelectronic device of claim 7, wherein the first semiconductor fin includes source and drain regions of a conductivity type complementary to source and drain regions in the third semiconductor fin, and wherein the second semiconductor fin includes source and drain regions of a conductivity type complementary to source and drain regions of the fourth semiconductor.

9. A microelectronic device, comprising:

a plurality of gate electrode stripes disposed over a plurality of semiconductor fins;

a plurality of isolation stripes substantially parallel to the plurality of gate electrode stripes and disposed between adjacent ones of the plurality of semiconductor fins, wherein the plurality of isolation stripes are self-aligned to the plurality of gate electrode stripes.

10. The microelectronic device of claim 9, wherein the plurality of gate electrode stripes and plurality of isolation stripes have a pitch that is an integer multiple of a minimum stripe pitch.

11. The microelectronic device of claim 9, wherein the plurality of gate electrode stripes is interdigitated with the plurality of isolation stripes to form a population of stripes of a fixed pitch.

12. A method of fabricating a microelectronic device, the method comprising:

receiving a semiconductor fin disposed over a substrate;

forming a gate electrode over the semiconductor fin; and

bifurcating the semiconductor fin at an isolation point that is self-aligned to the gate electrode.

13. The method of claim 12, wherein bifurcating the semiconductor fin at the isolation point further comprises defining dimensions of the gate electrode and dimensions of the isolation point with a single lithographic patterning mask.

14. The method of claim 13, wherein bifurcating the semiconductor fin at the isolation point further comprises removing a first portion of the semiconductor fin at the isolation point selectively to a second portion of the semiconductor fin over which the gate electrode is disposed.

15. The method of claim 13, wherein defining dimensions of the gate electrode and dimensions of the isolation point with a single lithographic patterning mask further comprises defining a plurality of gate electrode placeholders over the semiconductor fin.

16. The method of claim 13 further comprising removing a subset of the gate electrode placeholders to expose the first portion of the fin.

17. A method of fabricating a microelectronic device, the method comprising:

forming a plurality of sacrificial placeholders over a semiconductor fin;

removing a subset of the sacrificial placeholders;

removing a portion of the fin exposed by the placeholder removal;

depositing a dielectric material where fin portion was removed;

replacing a second subset of the sacrificial placeholders with a non-sacrificial gate stack.

18. The method of claim 17, wherein forming the plurality of sacrificial placeholders further comprises forming three placeholders over two semiconductor fins;

wherein removing the first subset of the sacrificial placeholders comprises removing a center one of the three sacrificial placeholders;

wherein removing a portion of the semiconductor fin exposed by the placeholder removal comprises bifurcating the semiconductor fin into first and second semiconductor fins; and

wherein replacing the second subset of sacrificial placeholders comprises;

removing a remaining two of the three sacrificial placeholders to form openings exposing second portions of the first and second semiconductor fins; and

forming a first and second gate stack over the second portions of the first and second semiconductor fins.

19. The method of claim 18, wherein removing a center one of the three sacrificial placeholders comprises masking off an outer pair of the three sacrificial placeholders.

20. The method of claim 18, wherein forming the plurality of sacrificial placeholders over the semiconductor fin further comprises printing a grating pattern of a fixed pitch.

21. The method of claim 17, wherein the plurality of semiconductor fins have a lattice mismatch with a substrate over which the fins are disposed, the lattice mismatch inducing a first level of stress in the fins;

and wherein the sacrificial placeholder maintains a second level of stress in the fins after removing the portion of the fin, wherein the second level of stress is at least 50% of the first level of stress.

22. The method of claim 22, wherein the plurality of semiconductor fins comprises a SiGe alloy and the substrate is a silicon substrate.

23. A mobile computing device, comprising:

a processor with circuitry employing non-planar transistors and through gate isolation;

a display screen;

an RF transmitter or receiver; and

an antenna.

24. The mobile computing device of claim 23, wherein the processor and RF transmitter or receiver are on a single integrated circuit (IC) as components of a system on a chip (SoC).