Methods, Apparatus, and Systems for Contacting Semiconductor Dies that are Electrically Coupled to Test Access Interface Positioned in Scribe Lines of a Wafer

• US 20140002122A1
• Filed: 06/30/2011
• Published: 01/02/2014
• Est. Priority Date: 06/30/2011
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Dibattista, Larry John, Gurley, Duncan Packard
• Granted Patent: US 9,632,109 B2
• Time in Patent Office: Days
• US Class Current: 324/750.24
• CPC Class Codes: G01R 1/0491 for testing integrated circuits on wafers, e.g. wafer-level test cartridge
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

A semiconductor device includes a first wafer having i) a plurality of semiconductor dies, ii) a plurality of scribe lines adjacent one or more of the semiconductor dies, iii) a test access interface positioned in one or more of the scribe lines, wherein the test access interface has a first plurality of through-substrate conductors with a standardized physical layout, and iv) electrical couplings between at least some of the through-substrate conductors and at least one of the semiconductor dies. Methods, apparatus and systems for testing this and other types of semiconductor devices are also disclosed.

Claims

1. A semiconductor device, comprising:

a first wafer having i) a first plurality of semiconductor dies, ii) a first plurality of scribe lines, each of the first plurality of scribe lines adjacent one or more of the first plurality of semiconductor dies, iii) a first test access interface positioned in one or more of the first plurality of scribe lines, the first test access interface having a first plurality of through-substrate conductors with a standardized physical layout, and iv) electrical couplings between at least some of the first plurality of through-substrate conductors and at least one of the first plurality of semiconductor dies.

2. The semiconductor device of claim 1, further comprising:

a second wafer stacked on the first wafer, the second wafer having i) a second plurality of semiconductor dies, ii) a second plurality of scribe lines, each of the second plurality of scribe ones adjacent one or more of the second plurality of semiconductor dies, iii) a second test access interface positioned in one or more of the second plurality of scribe lines, the second test access interface having a second plurality of through-substrate conductors with the standardized physical layout, and iv) electrical couplings between at least some of the second plurality of through-substrate conductors and at least one of the second plurality of dies; and

electrical couplings between the first test access interface and the second test access interface.

3. The semiconductor device of claim 1, further comprising:

a substrate having i) a set of one or more semiconductor die cut from a second wafer, ii) a set of one or more scribe lines, each of the set of one or more scribe lines adjacent at least one semiconductor the in the set of one or more semiconductor dies, iii) a second test access interface positioned in one or more of the set of one or more scribe lines, the second test access interface having a second plurality of through-substrate conductors with the standardized physical layout, and iv) electrical couplings between at least some of the second plurality of through-substrate conductors and at least one of the set of one or more semiconductor dies; and

electrical couplings between the first test access interface and the second test access interface.

4. The semiconductor device of claim 1, further comprising:

a second plurality of semiconductor dies, the second plurality of semiconductor dies being known good dies; and

electrical couplings between the first plurality of semiconductor dies and the second plurality of semiconductor dies.

5. The semiconductor device of claim 1, wherein at least some of the plurality of through-substrate conductors define a ground-shielded signal line.

6. The semiconductor device of claim 1, wherein the plurality of through-substrate conductors comprises through-silicon vias (TSVs).

7. A method for laying out elements on a wafer, comprising:

using a computer,

electronically specifying positions of a plurality of semiconductor dies on the wafer, the positions of the semiconductor dies defining scribe lines adjacent the semiconductor dies;

electronically selecting a test access interface from among a plurality of test access interfaces, the selected test access interface having a standardized physical layout that is independent of a physical layout of the semiconductor dies on the wafer;

electronically specifying a position of an instance of the selected test access interface with respect to the physical layout of the semiconductor dies on the wafer, the position causing the instance of the selected test access interface to be located in one or more of the scribe lines; and

electronically specifying a plurality of electrical couplings between the instance of the selected test access interface and at least one of the semiconductor dies.

8. The method of claim 7, wherein the electronically selected test access interface is one of the group consisting of:

a radio frequency (RF) interface, an audio interface, a video interface, an analog mixed signal interface, and a high-speed serial interface.

9. The method of claim 7, wherein the standardized physical layout of the selected test access interface defines a ground-shielded signal line.

10. Apparatus for contacting semiconductor dies during semiconductor test, the apparatus comprising:

a substrate having a first surface, a second surface opposite the first surface, a plurality of through-substrate conductors extending between the first surface and the second surface, a redistribution layer having electrical connections to the through-substrate conductors, and a plurality of probe sets coupled to the first surface, wherein each probe set has a standardized physical layout for contacting a corresponding scribe line test access interface on a wafer, each of the plurality of probe sets has a position with respect to the first substrate corresponding to a position of at least one scribe line on the wafer, and each of a number of probes in the probe sets is coupled to a respective one of the through-substrate conductors.

11. The apparatus of claim 10, wherein each probe set is part of a pre-designed brick, wherein the pre-designed brick dictates i) a placement of electrical contacts on the second surface of the substrate, and ii) electrical couplings between the through-substrate conductors and the electrical contacts by way of the redistribution layer.

12. The apparatus of claim 11, further comprising:

a probe head having probes for contacting a set of the electrical contacts corresponding to at least one of the probe sets; and

programmed robotics for moving the probe head in contact with the set of the electrical contacts.

13. The apparatus of claim 10, further comprising a switching matrix on the substrate, the switching matrix coupled to two or more of the probe sets by way of the through-semiconductor conductors and the redistribution layer.

14. The apparatus of claim 10, wherein the probe sets comprise through-silicon pillars.

15. The apparatus of claim 10, further comprising:

a plurality of second substrates, wherein each of the second substrates has a first surface, a second surface, and at least one of the probe sets extending from the first surface, wherein each of the second substrates is coupled to the first substrate with the second surface of the second substrate facing the first surface of the first substrate.

16. The apparatus of claim 15, further comprising:

electrical contacts on the second surface of the first substrate;

electrical couplings between the through-substrate conductors and the electrical contacts by way of the redistribution layer;

a probe head having probes for contacting a set of the electrical contacts corresponding to at least one of the probe sets; and

programmed robotics for moving the probe head in contact with the set of the electrical contacts.

17. The apparatus of claim 15, further comprising a switching matrix on the first substrate, the switching matrix coupled to two or more of the probe sets by way of the through-semiconductor conductors and the redistribution layer.

18. The apparatus of claim 15, wherein the probe sets comprise through-silicon pillars.

19. A method for contacting semiconductor dies during semiconductor test, the method comprising:

providing a wafer having a plurality of semiconductor dies, a plurality of scribe lines, and at least one test access interface, wherein each of the at least one test access interface has a plurality of through-substrate conductors that are electrically coupled to at least one of the semiconductor dies, and wherein the wafer has at least one pair of through-substrate conductors that are electrically coupled;

contacting the wafer with a space transformer having at least one probe set for contacting one or more of the at least one test access interface; and

verifying an alignment between at least one of the probe sets and at least one of the test access interfaces by performing a DC continuity loopback test using at least one pair of probes extending from the space transformer and the at least one pair of through-substrate conductors that are electrically coupled.

20. Apparatus for contacting semiconductor dies during semiconductor test, the apparatus comprising:

a plurality of probe heads, each having at least one probe set with a standardized physical layout for contacting a plurality of through-semiconductor conductors in a corresponding scribe line test access interface on a wafer.