System and Method for a Driver Circuit

• US 20140002141A1
• Filed: 08/29/2012
• Published: 01/02/2014
• Est. Priority Date: 06/30/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Barrenscheen, Jens, Beaurenaut, Laurent, Bachhuber, Marco, Bacigalupo, Tommaso, Nuebling, Marcus
• Granted Patent: US 8,710,873 B2
• Time in Patent Office: Days
• US Class Current: 327/108
• CPC Class Codes: H02M 1/0012 Control circuits using digital or numerical techniques in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches

Abstract

In accordance with an embodiment, a method of operating a gate driving circuit includes receiving a reference timing pulse, measuring the received timing pulse according to a local clock generator of the gate driving circuit, and generating a switching control signal based on the measured received timing pulse.

Claims

1. A method of operating a gate driving circuit, the method comprising:

receiving a reference timing pulse;

measuring the received timing pulse according to a local clock generator of the gate driving circuit; and

generating a switching control signal based on the measured received timing pulse.

2. The method according to claim 1, further comprising storing the measured received timing pulse in a memory.

3. The method according to claim 1, further comprising applying the switching control signal to a switching transistor.

4. The method according to claim 1, wherein generating the switching control signal based on the measured received timing pulse comprises:

operating in a normal mode comprising;

receiving a switching control signal transition from an inactive state to an active state,

activating a gate driver output a first time period after receiving the switching control signal transition from an active state to an inactive state, wherein the first time period is based on the measured received timing pulse,

receiving a switching control signal transition from the active state to the inactive state, and

deactivating the gate driver output immediately or the first time period after receiving the switching control signal transition from an active state to an inactive state.

5. The method according to claim 1, wherein generating the switching control signal based on the measured received timing pulse comprises:

operating in a high current state comprising

receiving a switching control signal transition from an active state to an inactive state,

changing an output voltage of a gate driver output from a first voltage to a second voltage based on receiving the control signal transition; and

after a first period of time based on the measured received timing pulse, changing the output voltage of the gate driver output from the second voltage to a third voltage, wherein the third voltage configured to deactivate the switching transistor.

6. The method according to claim 1, wherein the measuring the received timing pulse comprises using a state machine.

7. The method according to claim 1, wherein the steps of receiving and measuring are performed in a learning mode, and the step of generating is performed in a normal mode.

8. The method according to claim 7, further comprising:

receiving a learning mode activation command from a digital bus; and

operating the gate driving circuit in the learning mode in response to the learning mode activation signal.

9. The method according to claim 1, wherein measuring the received timing pulse comprises:

starting a counter at a beginning of the received timing pulse;

modifying the counter according to a frequency of the local clock generator; and

stopping the counter at an end of the received timing pulse.

10. The method according to claim 1, further comprising operating the local clock generator, operating comprising running a relaxation oscillator.

11. A circuit comprising:

a clock generator;

a state machine coupled to the clock generator; and

an output driver having an input coupled to a switching control signal output of the state machine, wherein the state machine is configured to

receive a reference timing pulse,

measure the received reference timing pulse according to the clock generator, and

modify the switching control signal based on the measured received reference timing pulse.

12. The circuit according to claim 11, wherein the clock generator, state machine and output driver are disposed on an integrated circuit.

13. The circuit according to claim 11, wherein the state machine comprises a counter configured to start modifying a counter value at a beginning of the received reference timing pulse and stop modifying the counter value at an end of the received reference timing pulse.

14. The circuit according to claim 13, further comprising a memory coupled to an output of the counter, wherein the memory is configured to store an output value of the counter.

15. The circuit according to claim 13, wherein the clock generator comprises a relaxation oscillator.

16. The circuit according to claim 13, wherein the output driver is configured to:

receive a switching control signal transition from an active state to an inactive state;

change an output voltage of a gate driver output from a first voltage to a second voltage based on receiving the control signal transition; and

after a first period of time based on the measured received reference timing pulse, change the output voltage of the gate driver output from the second voltage to a third voltage, wherein the third voltage configured to deactivate a switching transistor coupled to the gate driver output.

17. The circuit according to claim 13, wherein the output driver is configured to drive an integrated gate bipolar transistor (IGBT).

18. A switch driving circuit comprising:

an output driver configured to be coupled to a control node of a switching transistor; and

a control circuit coupled to the output driver, the control circuit configured to

measure a reference pulse from a switching control input in a first mode of operation, and

produce a first timing delay from the switching control input to an output of the output driver based on the measured reference pulse in a second mode of operation.

19. The switch driving circuit according to claim 18, further comprising a communication interface coupled to the control circuit and coupled to a digital interface, wherein the communication interface is configured to receive a configuration command from the digital interface and place the control circuit in the first mode of operation upon receipt of the configuration command.

20. The switch driving circuit according to claim 18, wherein the control circuit is further configured to:

change an output voltage of the output driver from a first voltage to a second voltage when the switching control input is de-asserted; and

after the first timing delay, change the output voltage of the output driver from the second voltage to a third voltage, wherein the third voltage configured to deactivate the switching transistor.

21. The switch driving circuit according to claim 20, wherein the output driver is configured to drive an integrated gate bipolar transistor (IGBT).

22. The switch driving circuit according to claim 18, further comprising a timing reference circuit, wherein the control circuit is configured to measure the reference pulse with respect to an output of the timing reference circuit.

23. The switch driving circuit according to claim 22, wherein the timing reference circuit comprises a relaxation oscillator.