NONVOLATILE MEMORY DEVICE PERFORMING GARBAGE COLLECTION

• US 20140003142A1
• Filed: 03/06/2013
• Published: 01/02/2014
• Est. Priority Date: 06/29/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, JOON-HO, GO, GWANG-OK, SHIN, KYUNG-HO, LEE, MI-HYANG
• Granted Patent: US 9,805,799 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2207/2236 Copy
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A nonvolatile memory device comprises a first area of single-level cells (SLCs) and a second area of multi-level cells (MLCs). The device determines whether a free block can be created by copying data between memory blocks of the first area. Upon determining that the free memory block can be created by copying data between the memory blocks of the first area, the device copies the data between the memory blocks of the first area to create the free memory block. Otherwise, the device selects at least one memory block from the first area and allocates the selected memory block as free memory block by copying the data stored in the selected memory block of the first area to the second area.

Claims

1. A method of managing a nonvolatile memory device comprising a first area of single-level cells (SLCs) and a second area of multi-level cells (MLCs), the method comprising:

determining whether a free block can be created by copying data between memory blocks of the first area;

upon determining that the free memory block can be created by copying data between the memory blocks of the first area, copying the data between the memory blocks of the first area to create the free memory block; and

upon determining that the free memory block cannot be created by copying data between the memory blocks of the first area, selecting at least one memory block from the first area and allocating the selected memory block as free memory block by copying the data stored in the selected memory block of the first area to the second area.

2. The method of claim 1, wherein the MLCs are 3-bit MLCs.

3. The method of claim 1, wherein each of the memory blocks comprises a plurality of pages, wherein each of the pages is a valid page, an invalid page, or a free page.

4. The method of claim 3, selecting the at least one memory block comprises selecting a first memory block having a minimum number of free pages among the memory blocks of the first area.

5. The method of claim 4, wherein allocating the selected memory block comprises allocating the first memory block as a free memory block by copying data of a valid page in the first memory block to the second area.

6. The method of claim 3, wherein generating the free memory block comprises:

selecting first and second memory blocks, wherein the number of valid pages of the first memory block is equal to or less than the number of free pages of the second memory block; and

generating the free memory block by copying the data stored in the valid pages to the free pages.

7. The method of claim 6, wherein the first memory block is a memory block having a minimum number of valid pages among the memory blocks of the first area.

8. The method of claim 3, wherein generating the free memory block comprises:

selecting first through third memory blocks, wherein the number of valid pages in the first and second memory blocks are less than or equal to the number of free pages in the third memory block; and

generating the free memory block by copying data stored in the valid pages of the first and second memory blocks to the free page of the third memory block.

9. The method of claim 1, wherein the nonvolatile memory is a NAND flash memory.

10. The method of claim 1, wherein the second area comprises 2-bit multi-level cells.

11. A nonvolatile memory device, comprising:

a nonvolatile memory comprising a first area of single level cells (SLCs) and a second area of multi-level cells (MLCs); and

a processor configured to manage operations for generating a free memory block by determining whether the free memory block can be created by copying data between memory blocks of the first area, upon determining that the free memory block can be created by copying data between the memory blocks of the first area, copying the data between the memory blocks of the first area to create the free memory block, and upon determining that the free memory block cannot be created by copying data between the memory blocks of the first area, selecting at least one memory block from the first area and allocating the selected memory block as free memory block by copying the data stored in the selected memory block of the first area to the second area.

12. The nonvolatile memory device of claim 11, wherein the second block comprises 3-bit MLCs.

13. The nonvolatile memory device of claim 11, wherein the processor allocates the free memory block by copying the data stored in a first memory block with the minimum free space where data is not stored, among the memory blocks of the first area, to the second area.

14. The nonvolatile memory device of claim 11, wherein the processor comprises a flash translation layer (FTL), wherein the FTL operates to generate or allocate the free memory block.

15. The nonvolatile memory device of claim 11, wherein the second area comprises 2-bit MLCs.

16. A method of managing a nonvolatile memory device comprising a first area of single-level cells (SLCs) and a second area of multi-level cells (MLCs), the method comprising:

determining whether a free block can be generated by copying data between memory blocks of the first area; and

generating the free block by copying data between memory blocks of the first area or between at least one memory block of the first area and at least one memory block of the second area based on the determination.

17. The method of claim 16, further comprising erasing the at least one memory block of the first area after copying data from the at least one memory block of the first area to the at least one memory block of the second area.

18. The method of claim 16, further comprising updating a flash translation layer (FTL) to reflect the generation of the free block.

19. The method of claim 16, further comprising selecting the at least one memory block of the first area according to a number of free pages in the at least one memory block.

20. The method of claim 19, wherein the at least one memory block of the first area is a memory block having a least number of free pages in the first area.