METHODS FOR EXTENDING THE EFFECTIVE VOLTAGE WINDOW OF A MEMORY CELL

• US 20140003152A1
• Filed: 07/02/2012
• Published: 01/02/2014
• Est. Priority Date: 07/02/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Sharon, Eran
• Granted Patent: US 8,988,942 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

Methods for operating a non-volatile storage system in which cross-coupling effects are utilized to extend the effective threshold voltage window of a memory cell and to embed additional information within the extended threshold voltage window are described. In some cases, additional information may be embedded within a memory cell storing the highest programming state if the memory cell is in a high boosting environment by splitting the highest programming state into two substates and programming the memory cell to one of the two substates based on the additional information. A memory cell may be in a high boosting environment if its neighboring memory cells are in a high programmed state. Additional information may also be embedded within a memory cell storing the lowest programming state if the memory cell is in a low boosting environment. The additional information may include error correction information.

Claims

1. A method for reading data from a non-volatile storage system, comprising:

determining a reliability value, the reliability value is associated with whether a target memory cell is within a high boosting environment;

generating a first bit based on sensing the target memory cell between a highest programming state of a plurality of programming states and a second highest programming state of the plurality of programming states;

generating a high bit based on sensing the target memory cell between a first substate of the highest programming state and a second substate of the highest programming state;

determining a stored data value based on the first bit, the high bit, and the reliability value; and

outputting the stored data value.

2. The method of claim 1, further comprising:

generating a second bit based on sensing the target memory cell between a lowest programming state of the plurality of programming states and a second lowest programming state of the plurality of programming states;

generating a low bit based on sensing the target memory cell between a first substate of the lowest programming state and a second substate of the lowest programming state; and

the determining a stored data value includes determining the stored data value based on the first bit, the high bit, the second bit, the low bit, and the reliability value.

3. The method of claim 1, wherein:

the determining a reliability value includes sensing one or more neighboring data values from one or more neighboring memory cells adjacent to the target memory cell.

4. The method of claim 1, wherein:

the determining a reliability value includes determining whether a neighboring memory cell of the target memory cell has been programmed to a programming state corresponding with an upper portion of a voltage window.

5. The method of claim 1, wherein:

the determining a reliability value includes sensing one or more neighboring data values associated with one or more neighboring memory cells of the target memory cell and determining a weighted average of the one or more neighboring data values based on coupling ratios associated with each of the one or more neighboring memory cells.

6. The method of claim 1, wherein:

the determining a reliability value includes determining a programming state of a neighboring memory cell adjacent to the target memory cell.

7. The method of claim 1, wherein:

the target memory cell comprises a multi-level memory cell.

8. The method of claim 1, wherein:

the first bit is associated with a first reliability value;

the high bit is associated with a second reliability value; and

the determining a stored data value includes determining the stored data value based on the first bit, the high bit, the first reliability value, and the second reliability value.

9. A method for writing data to a non-volatile storage system, comprising:

acquiring one or more data pages;

acquiring one or more additional data values;

determining a first target programming state of a plurality of programming states corresponding with a first portion of the one or more data pages;

determining a first data value of the one or more additional data values;

determining whether the first target programming state corresponds with a highest programming state of the plurality of programming states; and

programming a memory cell to a substate of the highest programming state based on the first data value in response to determining that the first target programming state corresponds with the highest programming state.

10. The method of claim 9, wherein:

the one or more data pages include a first page;

the one or more additional data values comprise ECC information associated with the first page;

the plurality of programming states corresponds with a plurality of threshold voltage distributions associated with the memory cell; and

the first portion includes a first bit of the first page.

11. The method of claim 9, further comprising:

determining a second target programming state of the plurality of programming states corresponding with a second portion of the one or more data pages, the second portion is different from the first portion;

determining a second data value of the one or more additional data values;

determining whether the second target programming state corresponds with a lowest programming state of the plurality of programming states; and

programming a second memory cell to a substate of the lowest programming state based on the second data value in response to determining that the second target programming state corresponds with the lowest programming state.

12. The method of claim 9, wherein:

the programming a memory cell includes performing foggy-fine programming.

13. The method of claim 9, wherein:

the programming a memory cell includes programming the memory cell to a highest substate of the highest programming state using open loop programming.

14. The method of claim 9, wherein:

the first data value comprises error correction information associated with each of the one or more data pages.

15. The method of claim 9, wherein:

the one or more additional data values include redundant parity bits.

16. The method of claim 9, wherein:

the memory cell comprises a multi-level memory cell.

17. A non-volatile storage system, comprising:

a semiconductor memory array, the semiconductor memory array includes a target memory cell; and

one or more managing circuits in communication with the semiconductor memory array, the one or more managing circuits determine a reliability value associated with whether the target memory cell is within a high boosting environment, the one or more managing circuits perform a first sensing of the target memory cell between a highest programming state of a plurality of programming states and a second highest programming state of the plurality of programming states, the one or more managing circuits perform a second sensing of the target memory cell between a first substate of the highest programming state and a second substate of the highest programming state, the one or more managing circuits determine a stored data value based on the first sensing and the second sensing, the one or more managing circuits determine the stored data value based on the reliability value.

18. The non-volatile storage system of claim 17, wherein:

the one or more managing circuits determine the reliability value by sensing one or more neighboring data values from one or more neighboring memory cells of the target memory cell.

19. The non-volatile storage system of claim 17, wherein:

the one or more managing circuits determine the reliability value by sensing one or more neighboring data values associated with one or more neighboring memory cells of the target memory cell and determining a weighted average of the one or more neighboring data values based on coupling ratios associated with each of the one or more neighboring memory cells.

20. The non-volatile storage system of claim 18, wherein:

the target memory cell comprises a multi-level memory cell; and

the stored data value comprises error correction information.

21. A method for reading data from a non-volatile storage system, comprising:

determining a reliability value, the reliability value is associated with whether a target memory cell is within a high boosting environment;

generating a second bit based on sensing the target memory cell between a lowest programming state of the plurality of programming states and a second lowest programming state of the plurality of programming states;

generating a low bit based on sensing the target memory cell between a first substate of the lowest programming state and a second substate of the lowest programming state;

determining a stored data value based on the second bit, the low bit, and the reliability value; and

outputting the stored data value.

22. A method for programming data to a group of cells in a non-volatile storage system, comprising:

acquiring one or more data pages;

determining for a first cell of the group of cells a first programming state of a set of programming states, the first programming state corresponds with at least a first portion of the one or more data pages, the first programming state resides outside a main voltage window of the first cell; and

programming the first cell to the first programming state, the first cell reaches the first programming state only if the first cell is within an appropriate boosting environment.

23. The method of claim 22, wherein:

the appropriate boosting environment comprises a high boosting environment.

24. The method of claim 22, wherein:

the determining for a first cell of the group of cells a first programming state of a set of programming states includes determining the first programming state based on the appropriate boosting environment of the first cell.

25. A method for reading data from a group of cells in a non-volatile storage system, comprising:

determining a read value associated with a first cell of the group of cells;

determining a boosting condition associated with the first cell;

determining a reliability value associated with the first cell, the reliability value is based on the read value and the boosting condition;

determining a stored data value based on the read value and the reliability value; and

outputting the stored data value.

26. The method of claim 25, wherein:

the determining a reliability value associated with the first cell includes determining if the read value resides in an edge state of a main voltage window of the first cell.