CELL ARRAY AND MEMORY DEVICE INCLUDING THE SAME

• US 20140003173A1
• Filed: 12/17/2012
• Published: 01/02/2014
• Est. Priority Date: 06/28/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: KU, Kie-Bong
• Granted Patent: US 8,811,100 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

A memory cell array includes a plurality of normal word lines arranged at a first pitch, a plurality of repair word lines arranged at a second pitch, and a dummy boundary word line configured to be arranged between an outermost normal word line and an outermost repair word line.

Claims

1. A memory cell array comprising:

a plurality of normal word lines arranged at a first pitch;

a plurality of repair word lines arranged at a second pitch; and

a dummy boundary word line arranged between an outermost normal word line and an outermost repair word line.

2. The memory cell array of claim 1, wherein pitches of he word lines are substantially equal to one another,

wherein the word lines include the plurality of normal word lines, the dummy boundary word line, and the plurality of repair word lines.

3. A memory cell array comprising:

a plurality of normal word lines arranged at a first pitch;

a plurality of repair word lines arranged at a second pitch;

a dummy boundary word line arranged between an outermost normal word line and an outermost repair word line; and

a plurality of dummy repair word lines arranged among adjacent repair word lines at a third pitch.

4. The memory cell array of claim 3, wherein pitches of word lines are substantially equal to one another,

wherein the word lines include the plurality of normal word lines, the dummy boundary word line, the plurality of repair word lines, and the plurality of dummy repair word lines.

5. A memory device comprising:

a cell array including a plurality of normal word lines arranged at a first pitch, a plurality of repair word lines arranged at a second pitch, and a dummy boundary word line arranged between an outermost normal word line and an outermost repair word line;

a row repair circuit configured to store a failed row address and compare an input row address with the stored failed row address; and

a row circuit configured to activate a normal word line corresponding to the input row address among the plurality of normal word lines in an active operation, and to activate a repair word line corresponding to the stored failed row address without activating the normal word line when the row circuit is notified of information indicating that the row address input from the row repair circuit coincides with the stored failed row address.

6. The memory device of claim 5, wherein pitches of word lines are substantially equal to one another,

wherein the word lines includes the plurality of normal word lines, the dummy boundary word line, and the plurality of repair word lines.

7. The memory device of claim 5, wherein the cell array further comprises:

a plurality of dummy repair word lines configured to be arranged among adjacent repair word lines at a third pitch.

8. The memory device of claim 7, wherein pitches of all word lines are substantially equal to one another,

wherein the word lines include the plurality of normal word lines, the dummy boundary word line, the plurality of repair word lines, and the plurality of dummy repair word lines.

9. A memory cell array comprising:

a plurality of normal word lines arranged at a first pitch;

a plurality of repair word lines arranged at a second pitch; and

a dummy boundary word line arranged between a normal word line and a repair word line adjacent to the normal word line.

10. The memory cell array of claim 9, wherein pitches of the word lines are substantially equal to one another,

wherein the word lines include the plurality of normal word lines, the dummy boundary word line, and the plurality of repair word lines.