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DIGITAL FREQUENCY DEMODULATOR WITH LOW POWER CONSUMPTION AND RELATED SYSTEM AND METHOD

  • US 20140003472A1
  • Filed: 06/28/2012
  • Published: 01/02/2014
  • Est. Priority Date: 06/28/2012
  • Status: Abandoned Application
First Claim
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1. An apparatus comprising:

  • a frequency counter configured to receive an input signal containing pulses and to output a count value identifying a number of pulses in the input signal during a specified time period, the specified time period encompassing multiple cycles of the input signal;

    a comparator configured to receive the count value from the frequency counter, compare the count value to a second value, and provide an output signal based on the comparison; and

    a data latch configured to latch the output signal, wherein the latched value of the output signal represents a demodulated data value.

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