TEST BENCH TRANSACTION SYNCHRONIZATION IN A DEBUGGING ENVIRONMENT

• US 20140005999A1
• Filed: 06/21/2013
• Published: 01/02/2014
• Est. Priority Date: 06/22/2012
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: AGARWALA, BADRUDDIN, Parikh, Tarak, Bhat, Vivek, Joshi, Neeraj
• Granted Patent: US 9,582,625 B2
• Time in Patent Office: Days
• US Class Current: 703/14
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

This application discloses a design verification tool to simulate a circuit design with a test bench to generate a simulated output for the circuit design and a simulation log corresponding to operation of the test bench during the simulation of the circuit design. The design verification tool can determine whether the simulated output for the circuit design is different than an expected output for the circuit design. A debug tool can synchronize the simulated output for the circuit design with test bench transactions from the simulation log that prompted the generation of the simulated output for the circuit design when the simulated output of the circuit design is different than the expected output of the circuit design.

Claims

1. A method comprising:

simulating, by a computing system, a circuit design with a test bench to generate a simulated output for the circuit design and a simulation log corresponding to operation of the test bench during the simulation of the circuit design;

determining, by the computing system, whether the simulated output for the circuit design is different than an expected output for the circuit design; and

synchronizing, by the computing system, the simulated output for the circuit design with test bench transactions from the simulation log that prompted the generation of the simulated output for the circuit design when the simulated output of the circuit design is different than the expected output of the circuit design.

2. The method of claim 1, further comprising parsing, by the computing system, the simulation log to extract the test bench transactions from the simulation log prior to the synchronization.

3. The method of claim 1, further comprising prompting, by the computing system, display of the test bench transactions and the simulated output for the circuit design in temporal synchronization with each other.

4. The method of claim 3, wherein the simulated output for the circuit design and the test bench transactions are displayed in a common window.

5. The method of claim 1, further comprising receiving, by the computing system, a selection corresponding to a time during the simulation of the circuit design, wherein prompting display of the test bench transactions and the simulated output for the circuit design is performed in response to the selection.

6. The method of claim 1, further comprising:

synchronizing, by the computing system, a source code for the test bench with the test bench transactions from the simulation log; and

prompting, by the computing system, display of the source code for the test bench and the test bench transactions in temporal synchronization with each other.

7. The method of claim 6, wherein the source code for the test bench and the test bench transactions are displayed in a common window.

8. The method of claim 6, further comprising receiving, by the computing system, a selection corresponding to a time during the simulation of the circuit design, wherein prompting display of the source code for the test bench and the test bench transactions is performed in response to the selection.

9. The method of claim 1, wherein the simulated output for the circuit design includes waveform data.

10. A system comprising:

a circuit design simulation tool configured to simulate a circuit design with a test bench and generate a simulated output for the circuit design and a simulation log corresponding to operation of the test bench during the simulation of the circuit design, wherein the circuit design simulation tool is configured to determine whether the simulated output for the circuit design is different than an expected output for the circuit design; and

a debug tool configured to synchronize the simulated output for the circuit design with test bench transactions from the simulation log that prompted the generation of the simulated output for the circuit design when the simulated output of the circuit design is different than the expected output of the circuit design.

11. The system of claim 10, wherein the debug tool is configured to parse the simulation log to extract the test bench transactions from the simulation log prior to the synchronization.

12. The system of claim 10, wherein the debug tool is configured to prompt display of the test bench transactions and the simulated output for the circuit design in temporal synchronization with each other.

13. The system of claim 12, wherein the simulated output for the circuit design and the test bench transactions are displayed in a common window.

14. The system of claim 12, wherein the debug tool is configured to identify a selection corresponding to a time during the simulation of the circuit design, and prompt display of the test bench transactions and the simulated output for the circuit design in response to the selection.

15. The system of claim 10, wherein the debug tool is configured to synchronize a source code for the test bench with the test bench transactions from the simulation log, and prompt display of the source code for the test bench and the test bench transactions in temporal synchronization with each other.

16. The system of claim 15, wherein the source code for the test bench and the test bench transactions are displayed in a common window.

17. The system of claim 15, wherein the debug tool is configured to identify a selection corresponding to a time during the simulation of the circuit design, and prompt display of the source code for the test bench and the test bench transactions in response to the selection.

18. The system of claim 10, wherein the simulated output for the circuit design includes waveform data.

19. A method comprising:

parsing, by a computing system, a simulation log corresponding to operation of a test bench during a simulation of a circuit design to extract test bench transactions from the simulation log; and

synchronizing, by the computing system, the test bench transactions from the simulation log with waveform data generated during the simulation of the circuit design; and

prompting, by the computing system, display of the test bench transactions and the simulated output for the circuit design in temporal synchronization with each other.

20. The method of claim 19, wherein the simulated output for the circuit design and the test bench transactions are displayed in a common window.

21. The method of claim 19, further comprising:

synchronizing, by the computing system, a source code for the test bench with the test bench transactions from the simulation log; and

prompting, by the computing system, display of the source code for the test bench and the test bench transactions in temporal synchronization with each other.

22. The method of claim 21, wherein the source code for the test bench and the test bench transactions are displayed in a common window.

23. The method of claim 21, further comprising receiving, by the computing system, a selection corresponding to a time during the simulation of the circuit design, wherein prompting display of the source code for the test bench and the test bench transactions is performed in response to the selection.

24. The method of claim 19, further comprising receiving, by the computing system, a selection corresponding to a time during the simulation of the circuit design, wherein prompting display of the test bench transactions and the waveform data for the circuit design is performed in response to the selection.

25. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:

parsing a simulation log corresponding to operation of a test bench during a simulation of a circuit design to extract test bench transactions from the simulation log; and

synchronizing the test bench transactions from the simulation log with waveform data generated during the simulation of the circuit design; and

prompting display of the test bench transactions and the simulated output for the circuit design in temporal synchronization with each other.

26. The apparatus of claim 25, wherein the simulated output for the circuit design and the test bench transactions are displayed in a common window.

27. The apparatus of claim 25, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising:

synchronizing a source code for the test bench with the test bench transactions from the simulation log; and

prompting display of the source code for the test bench and the test bench transactions in temporal synchronization with each other.

28. The apparatus of claim 27, wherein the source code for the test bench and the test bench transactions are displayed in a common window.

29. The apparatus of claim 27, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising receiving a selection corresponding to a time during the simulation of the circuit design, wherein prompting display of the source code for the test bench and the test bench transactions is performed in response to the selection.

30. The apparatus of claim 25, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising receiving a selection corresponding to a time during the simulation of the circuit design, wherein prompting display of the test bench transactions and the waveform data for the circuit design is performed in response to the selection.

31. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:

simulating a circuit design with a test bench to generate a simulated output for the circuit design and a simulation log corresponding to operation of the test bench during the simulation of the circuit design;

determining whether the simulated output for the circuit design is different than an expected output for the circuit design; and

synchronizing the simulated output for the circuit design with test bench transactions from the simulation log that prompted the generation of the simulated output for the circuit design when the simulated output of the circuit design is different than the expected output of the circuit design.

32. The apparatus of claim 31, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising parsing the simulation log to extract the test bench transactions from the simulation log prior to the synchronization.

33. The apparatus of claim 31, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising prompting display of the test bench transactions and the simulated output for the circuit design in temporal synchronization with each other.

34. The apparatus of claim 33, wherein the simulated output for the circuit design and the test bench transactions are displayed in a common window.

35. The apparatus of claim 31, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising receiving a selection corresponding to a time during the simulation of the circuit design, and wherein prompting display of the test bench transactions and the simulated output for the circuit design is performed in response to the selection.

36. The apparatus of claim 31, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising:

synchronizing a source code for the test bench with the test bench transactions from the simulation log; and

prompting display of the source code for the test bench and the test bench transactions in temporal synchronization with each other.

37. The apparatus of claim 36, wherein the source code for the test bench and the test bench transactions are displayed in a common window.

38. The apparatus of claim 36, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising receiving a selection corresponding to a time during the simulation of the circuit design, wherein prompting display of the source code for the test bench and the test bench transactions is performed in response to the selection.

39. The apparatus of claim 31, wherein the simulated output for the circuit design includes waveform data.