Method and Apparatus For Bus Lock Assistance

• US 20140006661A1
• Filed: 06/29/2012
• Published: 01/02/2014
• Est. Priority Date: 06/29/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chappell, Robert S., Gartler, Hermann W., Burns, David W., Faistl, John W., Tucknott, Michael D., Parathasarthy, Rajesh S.
• Granted Patent: US 9,524,263 B2
• Time in Patent Office: Days
• US Class Current: 710/105
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 12/1466 Key-lock mechanism
• CPC Class Codes: G06F 12/1491 in a hierarchical protection system, e.g. privilege levels, memory rings
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/602 Details relating to cache prefetching
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

Claims

1. A method, comprising:

detecting that an instruction of a thread is a locked instruction;

determining that execution of said instruction includes imposing a bus lock;

executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

2. The method of claim 1 wherein said determining that said execution of said instruction includes imposing a bus lock includes determining that said data item is not cacheable.

3. The method of claim 1 wherein said determining that said execution of said instruction includes imposing a bus lock includes determining that a memory type of said instruction does not permit cache locks.

4. The method of claim 1 wherein said determining that said execution of said instruction includes imposing a bus lock includes determining that a data item to be fetched by said instruction is not within a cache.

5. The method of claim 1 wherein said determining that said execution of said instruction includes imposing a bus lock includes determining that an address of a data item to be fetched by said instruction crosses a cache line boundary.

6. The method of claim 1 wherein said bus lock assistance function includes any of:

raising a flag to software;

dumping state of an instruction execution pipeline that executes said instruction;

preventing said bus lock from being imposed;

preventing said bus lock protocol from being followed.

7. The method of claim 7 further comprising detecting that bus lock assistance has been requested for said instruction as a pre-condition to executing said bus lock assistance function.

8. An apparatus, comprising:

instruction identification logic circuitry that identifies whether an instruction is a locked instruction;

bus lock assistance logic circuitry that identifies if bus lock assistance has been requested for said locked instruction;

first logic circuitry to determine if execution of said instruction includes imposition of a bus lock;

second logic circuitry to trigger a bus lock assistance function in response to a determination that said instruction is a bus lock instruction and that bus lock assistance has been requested, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

9. The apparatus of claim 8 wherein at least said instruction identification logic circuitry is embedded within an instruction execution pipeline.

10. The apparatus of claim 9 wherein said instruction identification logic circuitry is embedded within a stage of said instruction execution pipeline that performs instruction decoding.

11. The apparatus of claim 8 wherein said first logic circuitry is embedded within a memory execution unit of said instruction execution pipeline.

12. The apparatus of claim 8 wherein said second logic circuitry is embedded within a memory execution unit of said instruction execution pipeline.

13. The apparatus of claim 8 further comprising first register space that stores first information indicating if bus lock assistance has been requested, said bus lock assistance logic circuitry designed to read said first information.

14. The apparatus of claim 13 further comprising second register space that stores second information that indicates whether said instruction is a locked instruction, said locked instruction identification circuitry to write to said second register space.

15. The apparatus of claim 13 further comprising a unit of logic circuitry that requests bus lock assistance by writing to said first register space.

16. The apparatus of claim 8 wherein said bus lock assistance function includes any of:

raising a flag to software;

dumping state of an instruction execution pipeline that executes said instruction;

preventing said bus lock from being imposed;

preventing said bus lock protocol from being followed.

17. The apparatus of claim 16 wherein said bus lock assistance function is performed by any of:

dedicated logic circuitry

micro-code.

18. A machine readable medium containing program instructions that when processed by a processing core causes a method to be performed, said method comprising:

writing to register space of a processing core to indicate that bus lock assistance has been requested, said bus lock assistance being functionality associated with a bus lock other than implementation of a bus lock protocol;

receiving a flag from said processing core that indicates said bus lock assistance has been invoked.

19. The machine readable medium of claim 18 wherein said register space is model specific register space.

20. The machine readable medium of claim 18 wherein said program code is part of an application software program.

21. The machine readable medium of claim 18 wherein said program code is part of a virtual machine monitor (VMM).

22. The machine readable medium of claim 18 wherein said program code is part of an operating system.

23. The machine readable medium of claim 18 wherein said bus lock assistance includes any of the following:

dumping state of an instruction execution pipeline;

preventing said bus lock from being imposed;

preventing said bus lock protocol from being followed.