ROW HAMMER REFRESH COMMAND

• US 20140006703A1
• Filed: 06/30/2012
• Published: 01/02/2014
• Est. Priority Date: 06/30/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Zvika Greenfield
• Inventors: Bains, Kuljit S., Halbert, John B., Mozak, Christopher P., Schoenborn, Theodore Z., Greenfield, Zvika
• Granted Patent: US 9,236,110 B2
• Time in Patent Office: Days
• US Class Current: 711/106
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Abstract

A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Claims

1. A memory subsystem comprising:

hardware connectors to couple to a memory device having multiple rows of memory;

a memory controller coupled to the hardware connectors, the memory controller to

receive an indication via the hardware connectors that repeated access to a specific row of the memory device exceeds a threshold;

identify an address of the specific row; and

send a command to the memory device to perform a targeted refresh, the command to cause the memory device to perform a refresh targeted to a victim row physically adjacent to the identified row.

2. The memory subsystem of claim 1, wherein the memory controller is to identify the address by identifying a specific physical address for the specific row.

3. The memory subsystem of claim 1, wherein the memory controller is to identify the address by identifying a virtual address of the specific row that the memory device maps to a physical address of the physically adjacent row.

4. The memory subsystem of claim 1, wherein the memory controller is to identify the address by identifying an address of the specific row associated with the indication of repeated access, wherein the memory device identifies the physically adjacent row based on the address of the specific row associated with the indication of repeated memory access and a configuration of the memory device.

5. The memory subsystem of claim 1, wherein the memory controller is to identify the address by identifying a region of memory that includes the specific row, wherein the memory device refreshes the identified region, including the physically adjacent row.

6. The memory subsystem of claim 1, wherein the memory controller is to identify the address by identifying the address inside the command.

7. The memory subsystem of claim 6, wherein the command is embedded in an activation command for the memory device.

8. The memory subsystem of claim 1, wherein the memory controller to is further set a value in a Mode Register in conjunction with sending the command.

9. The memory subsystem of claim 1, wherein the memory controller is to send a sequence of commands to cause the memory device to perform the targeted refresh.

10. The memory subsystem of claim 9, wherein the memory controller is to send an activate command followed by a precharge command.

11. The memory subsystem of claim 9, wherein the memory controller is to send a targeted refresh command multiple times in sequence.

12. The memory subsystem of claim 11, wherein the memory controller is to send a different address with each of the targeted refresh commands in the sequence.

13. An electronic device comprising:

a memory subsystem having

a memory device to store data, the memory device including multiple rows of memory; and

a memory controller coupled to the memory device, the memory controller to receive an indication from the memory device that repeated access to a specific row of the memory device exceeds a threshold, identify an address of the specific row, and send a command to the memory device to perform a targeted refresh, the command to cause the memory device to perform a refresh targeted to a victim row physically adjacent to the identified row; and

a multicore processor coupled to the memory subsystem to access the memory subsystem during execution of the processor.

14. The device of claim 13, wherein the memory device comprises a dynamic random access memory (DRAM) device.

15. The device of claim 13, wherein the memory controller is to identify the address by identifying a specific physical address for the specific row.

16. The device of claim 13, wherein the memory controller is to identify the address by identifying a virtual address of the specific row that the memory device maps to a physical address of the physically adjacent row.

17. The device of claim 13, wherein the memory controller is to identify the address by identifying an address of the specific row associated with the indication of repeated access, wherein the memory device identifies the physically adjacent row based on the address of the specific row associated with the indication of repeated memory access and a configuration of the memory device.

18. The device of claim 13, wherein the memory controller is to identify the address by identifying a region of memory that includes the specific row, wherein the memory device refreshes the identified region, including the physically adjacent row.

19. The device of claim 13, wherein the memory controller is to identify the address by identifying the address inside the command.

20. The device of claim 19, wherein the command is embedded in an activation command for the memory device.

21. The device of claim 13, wherein the memory controller to is further set a value in a Mode Register in conjunction with sending the command.

22. The device of claim 13, wherein the memory controller is to send a sequence of commands to cause the memory device to perform the targeted refresh.

23. The device of claim 22, wherein the memory controller is to send an activate command followed by a precharge command.

24. The device of claim 22, wherein the memory controller is to send a targeted refresh command multiple times in sequence.

25. The device of claim 24, wherein the memory controller is to send a different address with each of the targeted refresh commands in the sequence.

26. A method comprising:

receiving an indication that repeated access to a specific row of memory in a memory device exceeds a threshold;

identifying an address of the row of memory; and

sending a command to the memory device to perform a targeted refresh, the command to cause the memory device to perform a refresh targeted to a row physically adjacent to the identified row.

27. The method of claim 26, wherein identifying the address comprises:

identifying a virtual address of the specific row that the memory device maps to a physical address of the physically adjacent row.

28. The method of claim 26, wherein identifying the address comprises:

identifying a region of memory that includes the specific row, wherein the memory device refreshes the identified region, including the physically adjacent row.

29. The method of claim 26, wherein identifying the address comprises:

identifying the address inside the command.

30. The method of claim 26, wherein sending the command comprises sending a sequence of commands to cause the memory device to perform the targeted refresh.