ROW HAMMER CONDITION MONITORING

• US 20140006704A1
• Filed: 06/30/2012
• Published: 01/02/2014
• Est. Priority Date: 06/30/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Zvika Greenfield
• Inventors: Bains, Kuljit S., Greenfield, Zvika, Schoenborn, Theodore Z., Mozak, Christopher P., Halbert, John B.
• Granted Patent: US 8,938,573 B2
• Time in Patent Office: Days
• US Class Current: 711/106
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 11/3471 Address tracing
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays

Abstract

A system monitors data accesses to specific rows of memory to determine if a row hammer condition exists. The system can monitor accessed rows of memory to determine if the number of accesses to any of the rows exceeds a threshold associated with risk of data corruption on a row of memory physically adjacent to the row with high access. Based on the monitoring, a memory controller can determine if the number of accesses to a row exceeds the threshold, and indicate address information for the row whose access count reaches the threshold.

Claims

1. A memory subsystem comprising:

hardware connectors to couple to a memory device having multiple rows of memory;

a memory controller coupled to the hardware connectors, the memory controller to monitor accesses to rows of a memory device for a time period;

determine if a number of accesses for any of the rows exceeds a threshold, the threshold associated with risk of data corruption on a row physically adjacent to the accessed row; and

indicate address information for one of the rows when the number of accesses to the row exceeds the threshold in the time period.

2. The memory subsystem of claim 1, wherein the memory controller is to couple to a dynamic random access memory (DRAM) device via the connectors.

3. The memory subsystem of claim 1, wherein the memory controller is to monitor accesses for a time period equal to a refresh cycle time for the memory device.

4. The memory subsystem of claim 1, wherein the memory controller is to monitor accesses by keeping a count for only a subset of all rows, and incrementing the count for the selected rows for each access.

5. The memory subsystem of claim 1, wherein the memory controller is to maintain a table of access counts to monitor the accesses, and is to compare the access counts to the threshold.

6. The memory subsystem of claim 5, wherein the memory controller is to sort the table by order of access count.

7. The memory subsystem of claim 5, wherein the memory controller is to determine a maximum victim count that indicates a maximum number of rows that could reach the threshold in the time period, and wherein a number of entries in the table is based on the maximum victim count.

8. The memory subsystem of claim 7, wherein if there are no empty entries in the table and a row is accessed that is not in the table, the memory controller is to replace the entry with a lowest-value access count with the accessed row, keep the previous access count for the entry, and increment the count for the entry.

9. The memory subsystem of claim 1, wherein the memory controller is to further trigger a targeted refresh command based on the row that exceeds the threshold, in response to determining the number of accesses to the row exceeds the threshold.

10. An electronic device comprising:

a memory subsystem having

a memory device to store data, the memory device including multiple rows of memory; and

a memory controller coupled to the hardware connectors, the memory controller to monitor accesses to rows of a memory device for a time period, determine if a number of accesses for any of the rows exceeds a threshold, the threshold associated with risk of data corruption on a row physically adjacent to the accessed row, and indicate address information for one of the rows when the number of accesses to the row exceeds the threshold in the time period; and

a multicore processor coupled to the memory subsystem to access the memory subsystem during execution of the processor.

11. The device of claim 10, wherein the memory controller is to monitor accesses for a time period equal to a refresh cycle time for the memory device.

12. The device of claim 10, wherein the memory controller is to monitor accesses by keeping a count for only a subset of all rows, and incrementing the count for the selected rows for each access.

13. The device of claim 10, wherein the memory controller is to maintain a table of access counts to monitor the accesses, and is to compare the access counts to the threshold.

14. The device of claim 13, wherein the memory controller is to determine a maximum victim count that indicates a maximum number of rows that could reach the threshold in the time period, and wherein a number of entries in the table is based on the maximum victim count.

15. The device of claim 14, wherein if there are no empty entries in the table and a row is accessed that is not in the table, the memory controller is to replace the entry with a lowest-value access count with the accessed row, keep the previous access count for the entry, and increment the count for the entry.

16. The device of claim 10, wherein the memory controller is to further trigger a targeted refresh command based on the row that exceeds the threshold, in response to determining the number of accesses to the row exceeds the threshold.

17. A method comprising:

monitoring accesses to rows of a memory device for a time period;

determining if a number of accesses for any of the rows exceeds a threshold, the threshold associated with risk of data corruption on a row physically adjacent to the accessed row; and

indicating address information for one of the rows when the number of accesses to the row exceeds the threshold in the time period.

18. The method of claim 17, wherein monitoring the accesses comprises monitoring accesses for a time period equal to a refresh cycle time for the memory device.

19. The method of claim 17, wherein monitoring the accesses further comprises keeping a count for only a subset of all rows, and incrementing the count for the selected rows for each access.

20. The method of claim 17, wherein monitoring the accesses further comprises maintaining a table of access counts to monitor the accesses, and comparing the access counts to the threshold.

21. The method of claim 20, wherein monitoring the accesses further comprises determining a maximum victim count that indicates a maximum number of rows that could reach the threshold in the time period, wherein a number of entries in the table is based on the maximum victim count.

22. The method of claim 21, wherein if there are no empty entries in the table and a row is accessed that is not in the table, monitoring the access with the table further comprises replacing the entry with a lowest-value access count with the accessed row, keeping the previous access count for the entry, and incrementing the count for the entry.

23. The method of claim 17, further comprising triggering a targeted refresh command based on the row that exceeds the threshold, in response to determining the number of accesses to the row exceeds the threshold.