LOW POWER LOW FREQUENCY SQUELCH BREAK PROTOCOL

• US 20140006826A1
• Filed: 06/30/2012
• Published: 01/02/2014
• Est. Priority Date: 06/30/2012
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wagh, Mahesh
• Application Number:
  US13/539,359
• Publication Number:
  US 20140006826A1
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatus for provision of a low power, low frequency squelch break protocol are described. In some embodiments, a fixed or variable time transmitter LFPS (Low Frequency Periodic Signaling) mechanism may be used that does not require a handshake and therefore much simpler in implementation than USB3 (Universal Serial Bus 3.0), for example. Also, an embodiment does not require a link common mode to be established and therefore may be optimized to support shorter durations for effecting exit from an electrical idle state that may be established via power-gating, for example. Other embodiments are also disclosed.

Claims

1. An apparatus comprising:

a first agent coupled to a second agent via a link; and

the first agent having controller logic to cause the link to exit from an electrical idle state in response to a Low Frequency Periodic Signaling (LFPS) signal,

wherein a transmit duration time of the LFPS signal is to be greater than a time it takes a receiver logic of the second agent to detect the LFPS signal.

2. The apparatus of claim 1, wherein the controller logic is to cause the link to exit from the electrical idle state without performing a handshake.

3. The apparatus of claim 1, wherein the controller logic is to cause the link to exit from the electrical idle state without establishment of a link common mode.

4. The apparatus of claim 1, wherein the controller logic is to wait for a timeout period when transitioning between two power states to reduce or avoid a race condition between LFPS signals and high power circuits being turned off on opposite ends of the link.

5. The apparatus of claim 1, wherein the first agent is to comprise a root complex to facilitate communication between the first agent and the second agent over the link.

6. The apparatus of claim 1, wherein the first agent is to comprise one or more of:

a processor core, a chipset, an input/output hub, or a memory controller.

7. The apparatus of claim 1, wherein the second agent is to comprise an input/output device.

8. The apparatus of claim 1, wherein the link is to comprise a point-to-point coherent interconnect.

9. The apparatus of claim 1, wherein the first agent is to comprise a plurality of processor cores and one or more sockets.

10. The apparatus of claim 1, wherein one or more of the first agent, the second agent, and the memory are on a same integrated circuit chip.

11. The apparatus of claim 1, wherein the link comprises a Peripheral Component Interconnect Express (PCIe) link.

12. The apparatus of claim 1, wherein the transmit duration time is to be between a minimum value and a maximum value.

13. The apparatus of claim 2, wherein the minimum value is about 600 ns and the maximum value is about 2 ms.

14. The apparatus of claim 1, wherein the transmit duration time is about 600 ns.

15. A method comprising:

receiving a Low Frequency Periodic Signaling (LFPS) signal over a link that couples a first agent to a second agent; and

causing the link to exit from an electrical idle state in response to the LFPS signal at a controller logic of the first agent,

wherein a transmit duration time of the LFPS signal is to be greater than a time it takes a receiver logic of the second agent to detect the LFPS signal.

16. The method of claim 15, further comprising the controller logic causing the link to exit from the electrical idle state without performing a handshake.

17. The method of claim 15, further comprising the controller logic causing the link to exit from the electrical idle state without establishment of a link common mode.

18. The method of claim 15, further comprising waiting for a timeout period when transitioning between two power states to reduce or avoid a race condition between LFPS signals and high power circuits being turned off on opposite ends of the link.

19. The method of claim 15, wherein the link comprises a Peripheral Component Interconnect Express (PCIe) link.

20. The method of claim 15, wherein the transmit duration time is between a minimum value and a maximum value.

21. A computing system comprising:

an input/output hub to couple a processor core and an input/output device via a link; and

the input/output hub having controller logic to cause the link to exit from an electrical idle state in response to a Low Frequency Periodic Signaling (LFPS) signal,

wherein a transmit duration time of the LFPS signal is to be greater than a time it takes a receiver logic to detect the LFPS signal.

22. The system of claim 21, wherein the controller logic is to cause the link to exit from the electrical idle state without performing a handshake.

23. The system of claim 21, wherein the controller logic is to cause the link to exit from the electrical idle state without establishment of a link common mode.

24. The system of claim 21, wherein the controller logic is to wait for a timeout period when transitioning between two power states to reduce or avoid a race condition between LFPS signals and high power circuits being turned off on opposite ends of the link.

25. The system of claim 21, wherein the input/output hub is to comprise a root complex to facilitate communication between the input/output device and the processor core over the link.

26. The system of claim 21, wherein the link is to comprise a point-to-point coherent interconnect.

27. The system of claim 21, wherein one or more of the processor core, the input/output hub, and a memory are on a same integrated circuit chip.

28. The system of claim 21, wherein the link comprises a Peripheral Component Interconnect Express (PCIe) link.

29. The system of claim 21, wherein the transmit duration time is to be between a minimum value and a maximum value.

30. The system of claim 21, wherein the transmit duration time is about 600 ns.