MEMORY CONTROLLER UTILIZING AN ERROR CODING DISPERSAL FUNCTION

• US 20140006900A1
• Filed: 08/30/2013
• Published: 01/02/2014
• Est. Priority Date: 07/31/2009
• Status: Active Grant

• Current Assignee: Pure Storage, Inc.
• Original Assignee: Cleversafe Incorporated (International Business Machines Corporation)
• Inventors: Grube, Gary W., Markison, Timothy W.
• Granted Patent: US 9,405,607 B2
• Time in Patent Office: Days
• US Class Current: 714/764
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/1092 Rebuilding, e.g. when physically replacing a failing disk
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

A memory controller comprises at least a memory control processing module and/or a distributed storage processing module. A method begins by the memory control processing module receiving a memory access request regarding a data segment. The method continues with the memory control processing module interpreting the memory access request to determine whether an error coding dispersal function of the data segment is applicable. The method continues with the memory control processing module sending the memory access request to the distributed storage processing module when the error coding dispersal function is applicable. The method continues with the distributed storage processing module performing the error coding dispersal function on the data segment to produce an error coded processed data segment. The method continues with the distributed storage processing module sending the error coded processed data segment to the memory control processing module.

Claims

1. A memory controller comprises:

a memory control processing module operable to;

receive a memory access request regarding a data segment;

interpret the memory access request to determine whether an error coding dispersal function of the data segment is applicable;

when the error coding dispersal function is applicable, send the memory access request to a distributed storage processing module; and

the distributed storage processing module operable to;

perform the error coding dispersal function on the data segment to produce an error coded processed data segment; and

send the error coded processed data segment to the memory control processing module.

2. The memory controller of claim 1 further comprises:

the memory control processing module is further operable to;

receive a read command of the data segment as the memory access request;

interpret the read command to determine that the data segment is storage as a plurality of data slices in accordance with the error coding dispersal function; and

address a plurality of memories to retrieve the plurality of data slices; and

the distributed storage processing module is further operable to;

perform the error coding dispersal function on the plurality of data slices to produce a reconstructed data segment as the error coded processed data segment.

3. The memory controller of claim 1 further comprises:

the memory control processing module is further operable to;

receive a write command of the data segment as the memory access request;

interpret the write command to determine that the data segment is to be stored as a plurality of data slices in accordance with the error coding dispersal function; and

address a plurality of memories to store the plurality of data slices; and

the distributed storage processing module is further operable to;

perform the error coding dispersal function on the data segment to produce the plurality of data slices as the error coded processed data segment.

4. The memory controller of claim 1 further comprises:

the memory control processing module is further operable to;

when the error coding dispersal function is not to be applied, convert a virtual memory address of the data segment to a non-distributed physical address;

when the error coding dispersal function is to be applied, send the memory access request to the distributed storage processing module; and

the distributed storage processing module is further operable to;

when the error coding dispersal function is applicable, convert the virtual memory address of the data segment to a plurality of distributed physical addresses.

5. The memory controller of claim 1, the distributed storage processing module further functions to:

interpret the memory access request to determine vault information; and

facilitate storage of the vault information.

6. The memory controller of claim 1 further comprises:

the memory interface operable to couple the distributed storage processing module to a main memory such that the distributed storage processing module communicates the error coded processed data segment with the main memory.

7. A memory control comprises:

an interface for coupling to a memory device; and

a processing module operably coupled to the interface and operable to;

receive a data segment memory transfer request from a first memory layer to a second memory layer;

determine whether the data segment is stored within the first memory layer in accordance with an error coding dispersal function;

when the data segment is stored in accordance with the error coding dispersal function, determine whether the data segment is to be stored in the second memory layer in accordance with the error coding dispersal function;

when the data segment is not to be stored in the second memory layer in accordance with the error coding dispersal function;

retrieve a plurality of data slices from the first memory layer;

convert a plurality of data slices into a reconstructed data segment;

determine whether to store the reconstructed data segment in accordance with a second error coding dispersal function in the second memory layer;

when the reconstructed data segment is to be stored in accordance with the second error coding dispersal function, perform the second error coding dispersal function on the reconstructed data segment to produce a second plurality of data slices; and

send the second plurality of data slices to the second memory layer.

8. The memory controller of claim 7, the processing module is further operable to receive a data segment memory transfer request by one of:

interpret a read request; and

interpret a write request.

9. The memory controller of claim 7, the processing module is further operable to:

when the data segment is to be stored in the second memory layer in accordance with the error coding dispersal function, facilitate forwarding of the plurality of data slices from the first memory layer to the second memory layer.

10. The memory controller of claim 7 further comprises:

the first memory layer including at least one of;

a main memory;

a local non-core memory;

a local area network memory;

a wide area network memory; and

the second memory layer including at least one of;

the main memory;

the local non-core memory;

the local area network memory; and

the wide area network memory.

11. The memory controller of claim 7, the processing module is further operable to:

when the data segment is not stored in accordance with the error coding dispersal function;

retrieve the data segment from the first memory layer;

determine whether to store the data segment in accordance with the second error coding dispersal function in the second memory layer;

when the data segment is to be stored in accordance with the second error coding dispersal function, perform the second error coding dispersal function on the data segment to produce the second plurality of data slices; and

send the second plurality of data slices to the second memory layer.

12. The memory controller of claim 7, the processing module is further operable to:

when the data segment is not stored in accordance with the error coding dispersal function;

retrieve the data segment from the first memory layer;

determine whether to store the data segment in accordance with the second error coding dispersal function in the second memory layer; and

when the data segment is not to be stored in accordance with the second error coding dispersal function, send the data segment to the second memory layer.

13. The memory controller of claim 7 further comprises:

a buffer to temporarily store the plurality of slices.