III-V COMPOUND SEMICONDUCTOR DEVICE HAVING METAL CONTACTS AND METHOD OF MAKING THE SAME

• US 20140008699A1
• Filed: 07/06/2012
• Published: 01/09/2014
• Est. Priority Date: 07/06/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: OXLAND, Richard Kenneth
• Granted Patent: US 8,866,195 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 21/28575 on semiconductor bodies comprising AIIIBV compounds
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/452 on AIII-BV compounds
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

semiconductor device comprises a semiconductor substrate; a channel layer of at least a first III-V semiconductor compound above the semiconductor substrate; a gate stack structure above a first portion of the channel layer; a source region and a drain region comprising at least a second III-V semiconductor compound above a second portion of the channel layer; and a first metal contact structure above the S/D regions comprising a first metallic contact layer contacting the S/D regions. The first metallic contact layer comprises at least one metal-III-V semiconductor compound.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a channel layer of at least a first III-V semiconductor compound above the semiconductor substrate;

a gate stack structure above a first portion of the channel layer;

a source region and a drain region above a second portion of the channel layer, the source and the drain (S/D) regions comprising at least a second III-V semiconductor compound; and

a first metal contact structure above the S/D regions comprising a first metallic contact layer contacting the S/D regions, the first metallic contact layer comprising at least one metal-III-V semiconductor compound.

2. The semiconductor device of claim 1, wherein the first metallic contact layer is partially embedded in the S/D regions.

3. The semiconductor device of claim 1, wherein the at least one metal-III-V semiconductor compound in the first metallic contact layer is a material of at least one metal and the at least second III-V semiconductor compound in the S/D regions.

4. The semiconductor device of claim 1, wherein the S/D regions further comprise a metal-III-V semiconductor compound.

5. The semiconductor device of claim 4, wherein the least one metal-III-V semiconductor compound in the first metallic contact layer and the metal-III-V semiconductor compound in the S/D regions are nickelide.

6. The semiconductor device of claim 1, wherein the first metal contact structure further comprises a diffusion barrier contacting the metallic contact layer, and a metal plug contacting the diffusion barrier.

7. The semiconductor device of claim 1, further comprising a spacer disposed along a side wall of the gate stack, wherein the S/D regions are recessed so that a portion of the S/D regions is below a bottom height of the spacer.

8. The semiconductor device of claim 1, further comprising a second metal contact structure above the gate stack structure, the second metal contact structure comprising a second metallic contact layer contacting the gate stack structure.

9. The semiconductor device of claim 8, wherein the gate stack structure is a metal, and the second metallic contact layer is disposed on the top surface of the gate structure.

10. The semiconductor device of claim 8, wherein the gate stack structure comprises polysilicon, and the second metallic contact layer comprises a silicide of a metal and is partially embedded in the gate stack structure.

11. The semiconductor device of claim 8, wherein the second metal contact structure further comprises a diffusion barrier contacting the second metallic contact layer, and a metal plug contacting the diffusion barrier.

12. A method for forming a semiconductor device which comprises:

providing a channel layer of at least one III-V semiconductor compound above a semiconductor substrate;

forming a gate stack structure above a first portion of the channel layer;

forming a source region and a drain (S/D) region above a second portion of the channel layer; and

forming a first metal contact structure above the S/D regions, wherein the first metal contact structure comprises a first metallic contact layer contacting the S/D regions, the first metallic contact layer comprising at least one metal-III-V semiconductor compound.

13. The method of claim 12, wherein forming a source region and a drain (S/D) region comprises forming a metallic material with a III-V semiconductor compound in the source region and the drain region.

14. The method of claim 13, forming a metallic material comprises:

providing at least one III-V semiconductor compound above the second portion of the channel layer; and

depositing a metal layer on the III-V semiconductor compound in the source region and the drain region, followed by a step of annealing the semiconductor device.

15. The method of claim 12, wherein providing a first metal contact structure above the S/D regions comprises:

forming a metal layer contacting the S/D regions;

forming a diffusion barrier contacting the metal layer; and

providing a metal plug contacting the diffusion barrier.

16. The method of claim 12, wherein providing a first metal contact structure above the S/D regions comprises a step of forming the first metallic contact layer comprising at least one metal-III-V semiconductor compound through a step of annealing.

17. The method of claim 12, further comprising forming a spacer along a side wall of the gate stack structure.

18. The method of claim 17, wherein forming the source region and the drain region above the second portion of the channel layer comprises disposing a portion of the source region and a portion of the drain region below a bottom height of the spacer.

19. The method of claim 12, wherein the gate stack structure comprises a metal or polysilicon.

20. The method of claim 12, wherein the forming of the first metal contact structure comprises

forming a metal layer onto the top surface of the gate stack structure;

forming a diffusion barrier contacting the metal layer;

filling the diffusion barrier with a metal plug; and

annealing the semiconductor device.

21. A semiconductor device comprising:

a semiconductor substrate;

a channel layer of at least a first III-V semiconductor compound above the semiconductor substrate;

a gate stack structure above a first portion of the channel layer;

a source region and a drain region above a second portion of the channel layer, the source and the drain (S/D) regions comprising at least a second III-V semiconductor compound;

a first metal contact structure above the S/D regions comprising a first metallic contact layer contacting the S/D regions, the first metallic contact layer comprising at least one metal-III-V semiconductor compound; and

a second metal contact structure above the gate stack structure, the second metal contact structure comprising a second metallic contact layer contacting the gate stack structure.

22. The semiconductor device of claim 21, wherein the gate stack structure comprises polysilicon, and the second metallic contact layer comprises a silicide of a metal.