PHOTONIC SEMICONDUCTOR DEVICES IN LLC ASSEMBLY WITH CONTROLLED MOLDING BOUNDARY AND METHOD FOR FORMING SAME
First Claim
1. A laminate leadless carrier package comprising:
- a photonic semiconductor chip;
a substrate supporting said photonic semiconductor chip, said substrate comprising a plurality of conductive and dielectric layers laminated together including a bottom conductive layer, a top conductive layer, and a dielectric layer between said top and bottom conductive layers;
a plurality of conductive slotted vias providing electrical connections between said top conductive layer and said bottom conductive layer;
a wire bond pad disposed on said top surface of said substrate;
a wire bond coupled to said photonic semiconductor chip and said wire bond pad; and
an encapsulation covering said photonic semiconductor chip, said wire bond, and at least a portion of said top surface of said substrate, wherein said encapsulation is a molding compound, and said molding compound is pulled back from at least one of said slotted vias,wherein said laminate leadless carrier package is arranged to be mounted in a side-looker configuration on a printed circuit board, said active area of said photonic semiconductor chip is perpendicular to said printed circuit board, and said slotted vias are arranged to be in electrical contact with said printed circuit board.
2 Assignments
0 Petitions
Accused Products
Abstract
Embodiments of a laminate leadless carrier package are presented. The package includes an optoelectronic chip, a substrate supporting the optoelectronic chip, a plurality of conductive slotted vias, a wire bond pad disposed on the top surface of the substrate, a wire bond coupled to the optoelectronic chip and the wire bond pad and an encapsulation covering the optoelectronic chip, the wire bond, and at least a portion of the top surface of the substrate. The slotted vias provide electrical connections between the top conductive layer and the bottom conductive layer. The substrate includes a plurality of conductive and dielectric layers laminated together including a bottom conductive layer, a top conductive layer, and a dielectric layer between the top and bottom conductive layers. The encapsulation is a molding compound, and the molding compound is pulled back from at least one of the slotted vias.
10 Citations
18 Claims
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1. A laminate leadless carrier package comprising:
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a photonic semiconductor chip; a substrate supporting said photonic semiconductor chip, said substrate comprising a plurality of conductive and dielectric layers laminated together including a bottom conductive layer, a top conductive layer, and a dielectric layer between said top and bottom conductive layers; a plurality of conductive slotted vias providing electrical connections between said top conductive layer and said bottom conductive layer; a wire bond pad disposed on said top surface of said substrate; a wire bond coupled to said photonic semiconductor chip and said wire bond pad; and an encapsulation covering said photonic semiconductor chip, said wire bond, and at least a portion of said top surface of said substrate, wherein said encapsulation is a molding compound, and said molding compound is pulled back from at least one of said slotted vias, wherein said laminate leadless carrier package is arranged to be mounted in a side-looker configuration on a printed circuit board, said active area of said photonic semiconductor chip is perpendicular to said printed circuit board, and said slotted vias are arranged to be in electrical contact with said printed circuit board. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A laminate leadless carrier package comprising:
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a photonic semiconductor chip; a substrate supporting said photonic semiconductor chip, said substrate comprising a plurality of conductive and dielectric layers laminated together including a bottom conductive layer, a top conductive layer, and a dielectric layer between said top and bottom conductive layers; a plurality of conductive slotted vias providing electrical connections between said top conductive layer and said bottom conductive layer; a wire bond pad positioned on said top surface of said substrate; and a wire bond coupled to said photonic semiconductor chip and said wire bond pad;
an encapsulation covering said photonic semiconductor chip, said wire bond, and at least a portion of said top surface of said substrate, wherein said encapsulation is a molding compound,wherein said molding compound is pulled back from a metal contact configured to mechanically and/or electrically connect the laminate leadless package to a printed circuit board, said laminate leadless carrier package is arranged to be mounted in a side-looker configuration on said printed circuit board, said active area of said photonic semiconductor chip is perpendicular to said printed circuit board, and in a top-looker configuration on a printed circuit board, and said active area of said photonic semiconductor chip is parallel to said printed circuit board.
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15. A process for manufacturing a plurality of laminate leadless carrier packages, comprising the steps of:
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preparing a substrate, wherein preparing said substrate comprises laminating a top conductive layer, a bottom conductive layer, and a dielectric layer between said top and bottom conductive layers together, and wherein said top conductive layer comprises a die attach pad, a wire bond pad, and at least two slotted vias; applying epoxy adhesive to said die attach pad; mounting a photonic semiconductor chip on said die attach pad; wire-bonding said photonic semiconductor chip with said wire bond pad using a wire bond; temporarily filling said slotted vias with temporary fillers; molding a molding compound to form an encapsulation covering said photonic semiconductor chip, said wire bond, and at least a portion of said top surface of said substrate; removing said temporary fillers from the slotted vias; and dicing said substrate into individual laminate leadless carrier packages. - View Dependent Claims (16, 17, 18)
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Specification