SYSTEMS AND METHODS FOR LOW-POWER LAMP COMPATIBILITY WITH A LEADING-EDGE DIMMER AND A MAGNETIC TRANSFORMER

• US 20140009079A1
• Filed: 03/13/2013
• Published: 01/09/2014
• Est. Priority Date: 07/03/2012
• Status: Active Grant

• Current Assignee: Signify Holding B.V. (Signify N.V.)
• Original Assignee: Cirrus Logic Incorporated
• Inventors: King, Eric Jerome, Melanson, John L., Xie, Yanhui
• Granted Patent: US 9,655,202 B2
• Time in Patent Office: Days
• US Class Current: 315/219
• CPC Class Codes: H05B 45/10 Controlling the intensity of the light
• CPC Class Codes: H05B 45/315 Reverse phase-control circuits
• CPC Class Codes: H05B 45/37 Converter circuits
• CPC Class Codes: H05B 47/17 Operational modes, e.g. switching from manual to automatic mode or prohibiting specific operations
• CPC Class Codes: Y02B 20/30 Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Abstract

A system and method for providing compatibility between a load and a secondary winding of a magnetic transformer driven at its primary winding by a trailing-edge dimmer may include determining from a magnetic transformer secondary signal a period of a half-line cycle of an output signal of the dimmer, determining from the magnetic transformer secondary signal an estimated occurrence of an end of a phase-cut angle of the dimmer, and generating a driving signal to the load based on the period and the estimated occurrence of the end of the phase-cut angle. A lamp assembly may include a lamp for generating light and a controller for controlling operation of the lamp, the controller comprising a timing control circuit for determining a period of a periodic signal received by the lamp assembly.

Claims

1. An apparatus comprising:

a controller to provide compatibility between a load and a secondary winding of a magnetic transformer driven at its primary winding by a trailing-edge dimmer, wherein the controller is configured to;

determine from a magnetic transformer secondary signal a period of a half-line cycle of an output signal of the dimmer;

determine from the magnetic transformer secondary signal an estimated occurrence of an end of a phase-cut angle of the dimmer; and

generate a driving signal to the load based on the period and the estimated occurrence of the end of the phase-cut angle.

2. The apparatus of claim 1, wherein the controller comprises a timing control circuit to determine the period of the half-line cycle of the output signal of the dimmer.

3. The apparatus of claim 2, wherein the timing control circuit comprises a phase-locked loop.

4. The apparatus of claim 2, wherein the timing control circuit comprises a delay-locked loop.

5. The apparatus of claim 1, the controller configured to determine the estimated occurrence of the end of the phase-cut angle based at least on a determination of an estimated time at which the magnetic transformer secondary signal exceeds a predetermined threshold magnitude.

6. The apparatus of claim 1, the controller configured to determine the estimated occurrence of the end of the phase-cut angle based at least on a determination of an estimated time at which the magnetic transformer secondary signal falls below a predetermined threshold magnitude.

7. The apparatus of claim 1, the controller configured to determine the estimated occurrence of the end of the phase-cut angle based on at least a determination of an estimated portion of the period in which the magnetic transformer secondary signal is greater than a predetermined threshold magnitude.

8. The apparatus of claim 1, wherein the load comprises a lamp and the driving signal is indicative of an intensity of light to be generated by the lamp.

9. The apparatus of claim 8, wherein the lamp comprises a light-emitting diode lamp.

10. The apparatus of claim 8, wherein the lamp comprises a lamp having a multifaceted reflector form factor.

11. A method for providing compatibility between a load and a secondary winding of a magnetic transformer driven at its primary winding by a trailing-edge dimmer comprising:

determining from a magnetic transformer secondary signal a period of a half-line cycle of an output signal of the dimmer;

determining from the magnetic transformer secondary signal an estimated occurrence of an end of a phase-cut angle of the dimmer; and

generating a driving signal to the load based on the period and the estimated occurrence of the end of the phase-cut angle.

12. The method of claim 11, further comprising determining the period of the half-line cycle of the output signal of the dimmer using a phase-locked loop.

13. The method of claim 11, further comprising determining the period of the half-line cycle of the output signal of the dimmer using a delay-locked loop.

14. The method of claim 11, further comprising determining the estimated occurrence of the end of the phase-cut angle based at least on a determination of an estimated time at which the magnetic transformer secondary signal exceeds a predetermined threshold magnitude.

15. The method of claim 11, further comprising determining the estimated occurrence of the end of the phase-cut angle based at least on a determination of an estimated time at which the magnetic transformer secondary signal falls below a predetermined threshold magnitude.

16. The method of claim 11, further comprising determining the estimated occurrence of the end of the phase-cut angle based at least on a determination of an estimated time at which the magnetic transformer secondary signal is greater than a predetermined threshold magnitude.

17. The method of claim 11, wherein the load comprises a lamp.

18. The method of claim 17, wherein the lamp comprises a light-emitting diode lamp.

19. The method of claim 17, wherein the lamp comprises a multifaceted reflector form factor.

20. A lamp assembly comprising:

a lamp for generating light; and

a controller for controlling operation of the lamp, the controller comprising a timing control circuit for determining a period of a periodic signal received by the lamp assembly, wherein the timing control circuit comprises one of a phase-locked loop and a delay-locked loop.

21. The lamp assembly of claim 20, wherein the lamp comprises a light-emitting diode lamp.

22. The lamp assembly of claim 20, wherein the lamp assembly comprises a multifaceted reflector form factor.