TESTING DEVICE

• US 20140009179A1
• Filed: 09/11/2012
• Published: 01/09/2014
• Est. Priority Date: 07/04/2012
• Status: Active Grant

• Current Assignee: Wistron Corporation
• Original Assignee: Wistron Corporation
• Inventors: Chen, Kuan-Han, Li, Quan, Wu, Yin-Ching
• Granted Patent: US 9,123,442 B2
• Time in Patent Office: Days
• US Class Current: 324/750.01
• CPC Class Codes: G06F 11/2221 to test input/output devices or peripheral units
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/022 in I/O circuitry

Abstract

A testing device including a first connector, a control unit, a first detecting circuit and a memory controller is provided. The first connector is electrically connected to a first bus. The control unit generates a plurality of first control signals according to a first enable signal from the first connector. The first detecting circuit is electrically connected to a plurality of first transmission lines in the first bus, and sequentially conducts the first transmission lines to a ground according to the first control signals. The memory controller detects states of the signals transmitted by the first transmission lines and determines whether to generate a first abnormal indication signal according to a detecting result. The control unit controls a plurality of indication lights according to the first abnormal indication signal.

Claims

1. A testing device, comprising:

a first connector, electrically connected to a first bus;

a control unit, generating a plurality of first control signals according to a first enable signal from the first connector;

a first detecting circuit, electrically connected to a plurality of first transmission lines in the first bus and sequentially conducting the first transmission lines to a ground according to the first control signals; and

a memory controller, detecting states of signals transmitted by the first transmission lines and determining whether to generate a first abnormal indication signal according to a detecting result, wherein the control unit controls a plurality of indication lights according to the first abnormal indication signal.

2. The testing device according to claim 1, further comprising:

a plurality of memories, electrically connected to the memory controller, wherein the memory controller accesses the memories according to an interface signal transmitted by the first bus.

3. The testing device according to claim 1, wherein the first detecting circuit comprises:

a plurality of first switches, respectively corresponding to the first transmission lines, and comprising first ends electrically connected to the first transmission lines and second ends electrically connected to the ground,

wherein the first detecting circuit sequentially turns on the first switches by the first control signals.

4. The testing device according to claim 1, wherein the first connector comprises a plurality of first power pins, the first detecting circuit respectively divides signals from the first power pins and generates a plurality of first divided signals accordingly, and the control unit compares the first divided signals with a first reference voltage and controls the indication lights according to a comparison result.

5. The testing device according to claim 4, wherein the first detecting circuit further comprises:

a plurality of first resistor strings, electrically connected between the first power pins and the ground and generating the first divided signals in response to the signals from the first power pins.

6. The testing device according to claim 1, wherein the first connector further comprises a plurality of first ground pins, the first detecting circuit detects signals from the first ground pins and generates a plurality of first detecting signals accordingly, and the control unit compares the first detecting signals with a second reference voltage and controls the indication lights according to a comparison result.

7. The testing device according to claim 6, wherein the first detecting circuit further comprises:

a plurality of first resistors, comprising first ends receiving a power voltage and second ends electrically connected to the first ground pins and generating the first detecting signals.

8. The testing device according to claim 1, further comprising:

a second connector, electrically connected to a second bus, and the control unit generating a plurality of second control signals according to a second enable signal from the second connector;

a second detecting circuit, electrically connected to a plurality of second transmission lines in the second bus and sequentially conducting the second transmission lines to the ground according to the second control signals; and

a bridge, electrically connected to the second bus, and the bridge detecting states of signals transmitted by the second transmission lines and determining whether to generate a second abnormal indication signal according to a detecting result, wherein the control unit controls the indication lights according to the second abnormal indication signal.

9. The testing device according to claim 8, further comprising:

a switch unit, electrically connected to the first bus and electrically connected to the bridge and the memory controller via a third bus and a fourth bus, wherein the control unit adjusts a level of a switch signal according to the first enable signal or the second enable signal, and the switch unit conducts one of the first bus and the third bus to the fourth bus according to the level of the switch signal, so as to enable the memory controller to access a plurality of memories according to an interface signal from the fourth bus.

10. The testing device according to claim 9, wherein the first connector, the first bus, the third bus, and the fourth bus conform to a first protocol;

the second connector and the second bus conform to a second protocol; and

the bridge converts a format of an interface signal transmitted by the second bus.

11. The testing device according to claim 8, wherein the second detecting circuit comprises:

a plurality of second switches, respectively corresponding to the second transmission lines and comprising first ends electrically connected to the second transmission lines and second ends electrically connected to the ground,

wherein the second detecting circuit sequentially turns on the second switches by the second control signals.

12. The testing device according to claim 8, wherein the second connector comprises a plurality of second power pins, the second detecting circuit respectively divides signals from the second power pins and generates a plurality of second divided signals accordingly, and the control unit compares the second divided signals with a first reference voltage and controls the indication lights according to a comparison result.

13. The testing device according to claim 12, wherein the second detecting circuit further comprises:

a plurality of second resistor strings, electrically connected between the second power pins and the ground and generating the second divided signals in response to the signals from the second power pins.

14. The testing device according to claim 8, wherein the second connector further comprises a plurality of second ground pins, the second detecting circuit detects signals from the second ground pins and generates a plurality of second detecting signals accordingly, and the control unit compares the second detecting signals with a second reference voltage and controls the indication lights according to a comparison result.

15. The testing device according to claim 14, wherein the second detecting circuit further comprises:

a plurality of second resistors, comprising first ends receiving a power voltage and second ends electrically connected to the second ground pins and generating the second detecting signals.