SPAC SERIES PROGRAMMABLE ARRAY OF CAPACITORS

• US 20140009248A1
• Filed: 07/05/2013
• Published: 01/09/2014
• Est. Priority Date: 07/05/2012
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Granger-Jones, Marcus
• Granted Patent: US 9,214,922 B2
• Time in Patent Office: Days
• US Class Current: 333/174
• CPC Class Codes: H01G 4/38 Multiple capacitors, i.e. structural combinations of fixed capacitors
• CPC Class Codes: H01G 4/40 Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
• CPC Class Codes: H01G 7/00 Capacitors in which the capacitance is varied by non-mechanical means; Processes of their manufacture
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 5/246 using electronic means H03J5/244 takes precedence

Abstract

A tunable series resonant circuit includes a voltage source, a source impedance, a variable capacitor, a series inductor, and a load impedance. The variable capacitor includes a sPAC (series programmable array of capacitors) having desirable characteristics for a tunable series resonant circuit. The sPAC may be a binary weighted sPAC, a thermometer coded sPAC, or some other sPAC.

Claims

1. A sPAC (series programmable array of capacitors) circuit comprising:

a first capacitor;

a second capacitor in series with the first capacitor;

a first switch in parallel with the first capacitor; and

a second switch in parallel with the second capacitor.

2. The sPAC circuit of claim 1, further comprising:

a first control node configured to control the first switch; and

a second control node configured to control the second switch.

3. The sPAC circuit of claim 1, wherein the sPAC is a binary weighted sPAC, and wherein the second capacitor has approximately half of a capacitance of the first capacitor.

4. The sPAC circuit of claim 1, wherein the sPAC is a thermometer coded sPAC, and wherein the second capacitor is approximately equal in capacitance to the first capacitor.

5. The sPAC circuit of claim 1, further comprising:

a source impedance in series with the sPAC; and

a series inductor in series with the sPAC.

6. The sPAC circuit of claim 5, further comprising:

an input voltage source.

7. The sPAC circuit of claim 5, further comprising:

a control portion configured to control the sPAC such that the sPAC circuit is matched to an external load.

8. The sPAC circuit of claim 5, wherein the sPAC is a binary weighted sPAC, and wherein the second capacitor has approximately half of the capacitance of the first capacitor.

9. The sPAC circuit of claim 5, wherein the sPAC is a thermometer coded sPAC, and wherein the second capacitor is approximately equal in capacitance to the first capacitor.

10. The sPAC circuit of claim 5, wherein the sPAC is configured to accept positive and negative control voltages.

11. The sPAC circuit of claim 10, wherein the first switch is a DC (direct current) coupled stacked switch including at least two FETs (Field Effect Transistors).

12. The sPAC circuit of claim 5, wherein the sPAC is not configured to accept negative control voltages.

13. The sPAC circuit of claim 12, wherein the first switch is a single supply stacked FET (Field Effect Transistor).

14. The sPAC circuit of claim 13, wherein:

the sPAc is binary coded;

the second capacitor has about one half of the capacitance of the first capacitor.

15. The sPAC circuit of claim 14, wherein the second capacitor has twice as many stacked FETs as the first capacitor has.

16. The sPAC circuit of claim 15, further comprising a first coupling capacitor located in series between the first capacitor and the second capacitor.

17. The sPAC circuit of claim 16, further comprising:

a third capacitor located in series with the second capacitor;

a third switch located in parallel with the third capacitor; and

a second coupling capacitor located in series between the second capacitor and the third capacitor.

18. The sPAC circuit of claim 17, wherein the third capacitor has a capacitance of approximately one fourth of the first capacitor, and wherein the third switch has approximately four times as many stacked FETs as the first switch.

19. The sPAC circuit of claim 18, further comprising a controller configured to control the switches.

20. The sPAC circuit of claim 5, further comprising a controller configured to control the switches.