CONFIGURABLE LANE ARCHITECTURE IN SOURCE SYNCHRONOUS SYSTEMS

• US 20140009633A1
• Filed: 07/05/2012
• Published: 01/09/2014
• Est. Priority Date: 07/05/2012
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Inventors: CHOPRA, Sanjeev, ADVANI, Hiten
• Granted Patent: US 8,686,754 B2
• Time in Patent Office: Days
• US Class Current: 348/222.1
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04N 23/00 Cameras or camera modules comprising electronic image sensors; Control thereof

Abstract

A system and method for utilizing multiple configurable lanes for clock and data transfer in source synchronous systems that may utilize a clock signal from another source for interpreting data received from the source. In an embodiment, a system may include a transmitter configured to transmit at least one clock signal and at least one data signal to a receiver device. The receiver device may have at least one clock lane and at least one data lane for receiving signals from the transmitter device. The clock lane(s) and data lane(s) can be arranged in any order as per requirement of system design. In the receiver, after manufacture, each data lane may be configured to be clocked by any clock lane.

Claims

1. A circuit, comprising:

a plurality of signal paths configured to receive a plurality of respective source synchronous signals;

a plurality of signal latch circuits; and

a configurable bus suited to couple any one of the plurality of signal paths to any one of the plurality of signal latch circuits.

2. The circuit of claim 1, wherein at least one of the plurality of signal paths comprises a clock signal path and wherein at least one of the plurality of the signal paths comprises a data path.

3. The circuit of claim 1, further comprising six signal paths such that four of the six signal paths comprise data signal paths and two of the six signal paths comprise clock signal paths.

4. The circuit of claim 1, wherein at least one of the plurality of signal paths comprises a differential signal path.

7. The circuit of claim 1, wherein each of the signal paths further comprise a receiver driver circuit coupled to a respective signal latch circuit.

5. A circuit, comprising:

a plurality of signal paths configured to receive a plurality of respective signals;

a plurality of signal latch circuits; and

a configurable bus suited to couple any one of the plurality of signal paths to any one of the plurality of signal latch circuits;

wherein each of the signal latch circuits further comprise;

a first flip-flop configured to latch a data signal on a rising edge of a first clock signal;

a second flip-flop configured to latch a data signal on a falling edge of a the clock signal;

a third flip-flop configured to latch a data signal on a rising edge of a second clock signal;

a fourth flip-flop configured to latch a data signal on a falling edge of a the second clock signal;

a first multiplexor having two inputs, a first input coupled to the output of the first flip-flop and a second input coupled to an output of the third flip-flop; and

a second multiplexor having two inputs, a first input coupled to an output of the second flip-flop and a second input coupled to an output of the fourth flip-flop.

6. The circuit of claim 5, further comprising a configuration logic circuit coupled to the first and second multiplexors, the configuration logic circuit suited to configure the multiplexors for selecting one of the two respective inputs to pass to an output.

8. An integrated circuit, comprising:

a plurality of lanes, each lane suited to receive one of a plurality of respective source synchronous signals via a respective driver circuit;

a plurality of signal latch circuits wherein each lane includes at least one signal latch circuit; and

a configurable bus suited to couple any one of the driver circuits to any one or more of the plurality of signal latch circuits.

10. The integrated circuit of claim 8 wherein at least one lane is configured as a source synchronous clock lane and wherein the configurable bus is configured to trigger at least one signal latch circuit with a signal received on the source synchronous clock lane.

11. The integrated circuit of claim 8 disposed on a single integrated circuit die.

12. The integrated circuit of claim 8 disposed on multiple integrated circuit dies.

9. (canceled)

13. A receiver, comprising:

a data receiver driver suited to receive a source synchronous data signal;

a first clock receiver driver suited to receive a first source synchronous clock signal;

a second clock receiver driver suited to receive a second source synchronous clock signal

a clock signal bus having a first bus line coupled to the first clock receiver driver and a second bus line coupled to the second clock receiver driver

a plurality of signal latch circuits having respective outputs coupled to at least one selection circuit, at least one latch circuit in the plurality of latch circuit suited to latch a data signal as triggered by the first source synchronous clock signal, and at least one latch circuit in the plurality of latch circuits suited to latch a data signal as triggered by the second source synchronous clock signal; and

a configuration circuit coupled to each selection circuit, the configuration circuit configured to select either the data signal latched by the first source synchronous clock signal or the data signal latched by the second source synchronous clock signal.

14. The receiver of claim 13, wherein the configuration circuit comprises firmware stored in a memory.

15. The receiver of claim 13, wherein the source synchronous data signal is latched by a signal latch circuit within 50 picoseconds of being received by the data receiver driver.

16. A system;

comprising;

a processor;

a transmitter circuit coupled to the processor and configured to transmit data signals and clock signals; and

a receiver circuit coupled to the processor and coupled to the transmitter and configured to receive the transmitted clock signals and the transmitted data signals, the receiver further comprising;

at least one data receiver driver suited to receive at least one data signal;

at least two clock receiver drivers suited to receive at least one first clock signal and at least one second clock signal, respectively;

a first data latch circuit configured to latch the at least one data signal in conjunction with the first clock signal; and

a second data latch circuit configured to latch the at least one data signal in conjunction with the second clock signal

a configuration circuit coupled to the first and second latch circuits and configured to select the latched data signal as latched by either the first or second clock signal.

17. The system of claim 16, further comprising a mobile device wherein the transmitter circuit comprises a camera and the receiver circuit comprises an image processing device.

18. A method, comprising:

receiving a first clock signal from a source synchronous transmitter;

receiving a second clock signal from a source synchronous transmitter

receiving a data signal from the source synchronous transmitter;

latching the data signal with the first clock signal at a data latch circuit; and

latching the data signal with the second clock signal at the data latch circuit.

19. A method, comprising:

receiving a plurality of clock signals from a source synchronous transmitter;

receiving a plurality of data signals from the source synchronous transmitter;

configuring a clock signal bus to route each of the plurality of clock signals to each of a plurality of data latch circuits.

20. The method of claim 19, wherein the routing does not impact a skew budget.