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IC LAYOUT PATTERN MATCHING AND CLASSIFICATION SYSTEM AND METHOD

  • US 20140010436A1
  • Filed: 09/11/2013
  • Published: 01/09/2014
  • Est. Priority Date: 02/12/2009
  • Status: Active Grant
First Claim
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1. A method for classifying patterns in a set of layout patterns, comprising:

  • computing a plurality of moments for each of a plurality of pattern windows of an integrated circuit layout; and

    classifying the pattern windows into pattern classes using a distance computation for respective moments of the pattern windows.

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