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HYBRID MEMORY WITH ASSOCIATIVE CACHE

  • US 20140013025A1
  • Filed: 07/06/2012
  • Published: 01/09/2014
  • Est. Priority Date: 07/06/2012
  • Status: Active Grant
First Claim
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1. A device, comprising:

  • a primary memory comprising a host memory space arranged as memory sectors corresponding to host logical block addresses (LBAs);

    a secondary memory implemented as a cache for the primary host memory; and

    a hybrid controller configured map clusters of host LBAs to clusters of solid state drive (SSD) LBAs, the SSD LBAs corresponding to a memory space of the cache, the mapping of the host LBA clusters to the SSD LBA clusters being fully associative wherein any host LBA cluster can be mapped to any SSD LBA cluster.

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