NONVOLATILE RANDOM ACCESS MEMORY AND DATA MANAGEMENT METHOD

• US 20140013034A1
• Filed: 05/13/2013
• Published: 01/09/2014
• Est. Priority Date: 07/09/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Oh-Seong Kwon
• Inventors: KWON, OH-SEONG, OH, JIHYUK
• Granted Patent: US 9,110,784 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1417 Boot up procedures
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/202 Non-volatile memory

Abstract

A data management method for a main memory including a memory controller and a nonvolatile RAM includes; designating code page data temporarily stored in a standby area of the nonvolatile RAM as set, copying the code page data from the standby area to an in-use area of the nonvolatile RAM, designating the code page data stored in the in-use area as reset, and thereafter, during rebooting of a user device incorporating the main memory, invalidating the reset code page data while retaining the set code page data in the nonvolatile RAM.

Claims

1. A data management method for a main memory including a memory controller and a nonvolatile RAM, the method comprising:

designating code page data temporarily stored in a standby area of the nonvolatile RAM as set;

copying the code page data from the standby area to an in-use area of the nonvolatile RAM;

designating the code page data stored in the in-use area as reset; and

thereafter, during rebooting of a user device incorporating the main memory, invalidating the reset code page data while retaining the set code page data in the nonvolatile RAM.

2. The method of claim 1, wherein the code page data is designated set and reset in accordance with register bits respectively associated with each code page in the code page data.

3. The method of claim 2, wherein a register bit respectively associated with each code page is stored with the code page in the nonvolatile RAM.

4. The method of claim 2, wherein the register bits are collectively stored in the memory controller.

5. The method of claim 2, wherein the register bits are collectively stored in a register of the memory controller.

6. The method of claim 1, wherein the main memory of the user device is incorporated within a Central Processing Unit (CPU).

7. The method of claim 1, further comprising:

copying the code page data from an auxiliary storage and writing the code page data in the standby area of the nonvolatile RAM.

8. The method of claim 1, further comprising:

detecting a power-off command; and

upon detecting a power-off command, collecting all code pages in the code page data designated as set into a predetermined area of the nonvolatile RAM.

9. The method of claim 1, further comprising:

setting a maximum size for the standby area of the nonvolatile RAM.

10. The method of claim 1, further comprising:

generating a data page upon execution of a code page in the code page data; and

storing the data page in a modified area of the nonvolatile RAM, wherein the data page is designated as reset.

11. A data management method for a main memory including a memory controller and a nonvolatile RAM, the method comprising:

executing a power-on routine in a user device incorporating the main memory;

determining whether the nonvolatile RAM is reset enabled;

upon determining that the nonvolatile RAM is reset enabled, invalidating code page data designated as reset while retaining the code page data designated as set in the nonvolatile RAM, and then loading an operating system from an auxiliary storage to the nonvolatile RAM, else

upon determining that the nonvolatile RAM is not reset enabled, loading the operating system from the auxiliary storage to the nonvolatile RAM.

12. The method of claim 11, wherein the code page data is designated as set upon being temporarily stored in a standby area of the nonvolatile RAM when copied from the auxiliary storage, and the code page data is designated as reset upon being moved from the standby area to an in-use area of the nonvolatile RAM prior to execution.

13. The method of claim 12, wherein the code page data is designated set and reset in accordance with register bits respectively associated with each code page in the code page data.

14. The method of claim 13, wherein a register bit respectively associated with each code page is stored with the code page in the nonvolatile RAM.

15. The method of claim 14, wherein the register bits are collectively stored in the memory controller.

16. A data management method for a main memory including a memory controller and a nonvolatile RAM, the method comprising:

executing a power-on routine in a user device incorporating the main memory;

determining whether the user device was abnormally powered-down;

upon determining that the user device was abnormally powered-down, invalidating code page data designated as reset while retaining the code page data designated as set in the nonvolatile RAM, and then loading an operating system from an auxiliary storage to the nonvolatile RAM, else

upon determining that the user device was not abnormally powered-down, executing the operating system without regard to the set and reset designation of the code page data stored in the nonvolatile RAM.

17. The method of claim 16, wherein the code page data is designated as set upon being temporarily stored in a standby area of the nonvolatile RAM when copied from the auxiliary storage, and the code page data is designated as reset upon being moved from the standby area to an in-use area of the nonvolatile RAM prior to execution.

18. The method of claim 16, wherein the code page data is designated set and reset in accordance with register bits respectively associated with each code page in the code page data.

19. The method of claim 18, wherein a register bit respectively associated with each code page is stored with the code page in the nonvolatile RAM.

20. The method of claim 18, wherein the register bits are collectively stored in the memory controller.