MEMORY SUB-SYSTEM AND COMPUTING SYSTEM INCLUDING THE SAME

• US 20140013066A1
• Filed: 07/01/2013
• Published: 01/09/2014
• Est. Priority Date: 07/05/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dong-Hwi, LIM, SUN-YOUNG
• Granted Patent: US 9,244,824 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/382 using universal interface adapter
• CPC Class Codes: G06F 3/0602 specifically adapted to achieve a particular effect
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory sub-system includes a main memory, a storage device, a control unit, and a common interface unit. The control unit is configured to control the main memory and the storage device. The common interface unit is operatively coupled to the control unit, and is configured to access the main memory and the storage device through the control unit in response to a request received from a host.

Claims

1. A memory sub-system, comprising:

a main memory;

a storage device;

a control unit configured to control the main memory and the storage device; and

a common interface unit operatively coupled to the control unit, wherein the common interface unit is configured to access the main memory and the storage device through the control unit in response to a request from a host.

2. The memory sub-system of claim 1, wherein the control unit is configured to control the main memory and the storage device based on a command included in a request packet received from the host.

3. The memory sub-system of claim 2, wherein a first data packet following the request packet is an extended request packet, and the control unit is configured to control the main memory and the storage device based on an extended command included in an extended header of the extended request packet when the command corresponds to an extended memory operation.

4. The memory sub-system of claim 3, wherein the request packet and the extended request packet each comprise a payload, the payload of the extended request packet comprises a source address indicating a source area in which data is stored, and the payload of the request packet comprises a destination address indicating a target area in which the data is to be stored, when the extended command corresponds to a memory copy operation that copies the data stored in the main memory or in the storage device.

5. The memory sub-system of claim 4, wherein the source address designates a first area in the main memory and the destination address designates a second area in the storage device.

6. The memory sub-system of claim 4, wherein the source address designates a first area in the storage device and the destination address designates a second area in the main memory.

7. The memory sub-system of claim 4, wherein the source address designates a first area in the main memory and the destination address designates a second area in the main memory, wherein the second area is different from the first area.

8. The memory sub-system of claim 3, wherein the control unit is configured to control the storage device by mapping at least one page of the storage device to an area of the main memory.

9. The memory sub-system of claim 8, wherein the control unit is configured to synchronize a first map of the storage device with a second map of the main memory using a synchronization command included in the extended command, or desynchronize the first map of the storage device with the second map of the main memory using a desynchronization command included in the extended command.

10. The memory sub-system of claim 8, wherein the control unit is configured to map at least one page address of the storage device to a physical address of the main memory, and the host is configured to directly manage the physical address of the main memory, wherein the physical address of the main memory is allocated to the host.

11. The memory sub-system of claim 8, wherein the control unit further comprises a buffer, the control unit is configured to map at least one page address of the storage device to a buffer address of the buffer, and the host is configured to manage a virtual address of the main memory mapped to the buffer address.

12. The memory sub-system of claim 1, wherein the control unit is configured to perform a swap operation that stores at least one page loaded in the main memory in the storage device when a new page is to be allocated in the main memory and the main memory does not include an unused physical page.

13. The memory sub-system of claim 1, wherein the control unit further comprises a special function register configured to store information indicating an initial setting of the storage device.

14. The memory sub-system of claim 1, wherein the main memory comprises one of a dynamic random access memory, a static random access memory, a phase-change random access memory, and a ferroelectric random access memory, and the storage device comprises a flash memory.

15. A computing system, comprising:

a host comprising a processor; and

a memory sub-system operatively coupled to the host, wherein the memory sub-system is configured to execute a request received from the host, wherein the memory sub-system comprises;

a main memory;

a storage device;

a control unit configured to control the main memory and the storage device; and

a common interface unit operatively coupled to the control unit, wherein the common interface unit is configured to access the main memory and the storage device through the control unit in response to the request received from the host.

16. The computing system of claim 15, wherein the control unit is configured to control the main memory and the storage device based on a command included in a request packet received from the host.

17. The computing system of claim 16, wherein a first data packet following the request packet is an extended request packet, and the control unit is configured to control the main memory and the storage device based on an extended command included in an extended header of the extended request packet when the command corresponds to an extended memory operation.

18. An interface unit for a computing system, comprising:

a decoder, comprising;

a header parser configured to extract a header from a packet received from a host, analyze the extracted header, and provide a command to a control unit of a memory sub-system in the computing system, and

a payload detector configured to detect a payload in the packet received from the host, and provide the detected payload to the control unit; and

an encoder, comprising;

a header generator configured to generate a header of a packet to be transmitted to the host based on an output received from the control unit, and

a payload generator configured to generate a payload of the packet to be transmitted to the host based on the output received from the control unit, wherein the interface unit is disposed in the memory sub-system, and is configured to access a main memory and a storage device in the memory sub-system through the control unit,

wherein the control unit is configured to control the main memory and the storage device based on the command.

19. The interface unit of claim 18, wherein the decoder further comprises:

an extended header parser configured to extract an extended header from an extended request packet received from the host, analyze the extracted extended request header, and provide an extended command to the control unit,

wherein the control unit is configured to control the main memory and the storage device based on the extended command when the command corresponds to an extended memory operation.

20. The interface unit of claim 18, wherein the payload of the packet received from the host and the payload of the packet to be transmitted to the host each comprise an address and data.