DEBUG ARCHITECTURE

• US 20140013172A1
• Filed: 07/09/2013
• Published: 01/09/2014
• Est. Priority Date: 07/09/2012
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: UltraSoC Technologies Ltd (Siemens AG)
• Inventors: Hopkins, Andrew Brian Thomas
• Granted Patent: US 9,026,871 B2
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G06F 11/3656 using a specific debug interface

Abstract

Roughly described, a method of controlling transportation of debug data on an integrated circuit chip, the integrated circuit chip comprising a shared hub and a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, wherein between each respective debug unit and the shared hub there is an interface configured to transport data messages over each of a plurality of flows, the flows being assigned priorities, the method comprising: transporting control data for controlling the state of a debug unit on a priority flow having a first priority; and transporting debug data output by a debug unit as a result of debugging the peripheral circuit connected to that debug unit on a flow having a second priority, wherein the first priority is higher than the second priority.

Claims

1. A method of controlling transportation of debug data on an integrated circuit chip, the integrated circuit chip comprising a shared hub and a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, wherein between each respective debug unit and the shared hub there is an interface configured to transport data messages over each of a plurality of flows, the flows being assigned priorities, the method comprising:

transporting control data for controlling the state of a debug unit on a priority flow having a first priority; and

transporting debug data output by a debug unit as a result of debugging the peripheral circuit connected to that debug unit on a flow having a second priority, wherein the first priority is higher than the second priority.

2. A method as claimed in claim 1, wherein if at any time the data to be transported on the interface exceeds the bandwidth of the interface, data on a flow having a higher priority than another flow is transported in preference to data on that other flow.

3. A method as claimed in claim 1, wherein the shared hub comprises a buffer, and the method further comprising at the shared hub storing data from a flow having a higher priority than another flow in preference to data from that other flow.

4. A method as claimed in claim 3, further comprising discarding data from a flow having a third priority in the buffer in order to store data from a flow having a fourth priority in the buffer, wherein the fourth priority is higher than the third priority.

5. A method as claimed in claim 1, wherein the shared hub comprises a physical buffer comprising a plurality of logical buffers, the method comprising at the shared hub storing data from different flows in different logical buffers.

6. A method as claimed in claim 1, further comprising transporting data from different debug units on different flows.

7. A method as claimed in claim 1, wherein the integrated circuit chip is configured to communicate with a plurality of debuggers, the method further comprising transporting data destined for different debuggers on different flows.

8. A method as claimed in claim 1, further comprising, at each debug unit:

receiving one of a plurality of throttle levels, each throttle level indicating a respective quantity of debug data to be accumulated by specifying a respective type of debug data to be accumulated;

reconfiguring the debug unit to accumulate the specified type of debug data; and

accumulating the specified type of debug data.

9. A method as claimed in claim 8, comprising reconfiguring the debug unit by setting filters to detect a range of data indicated by the throttle level.

10. A method as claimed in claim 8, comprising reconfiguring the debug unit by setting a trigger to detect an event indicated by the throttle level.

11. A method as claimed in claim 8, further comprising receiving an instruction of the flow to output the accumulated debug data on.

12. A method as claimed in claim 8, further comprising, at each debug unit:

receiving a further throttle level indicating a respective quantity of further debug data to be accumulated by specifying a respective further type of debug data to be accumulated;

reconfiguring the debug unit to accumulate the specified further type of debug data; and

accumulating the specified further type of debug data.

13. A method as claimed in claim 12, further comprising receiving a further instruction of the flow to output the accumulated further debug data on, the accumulated further debug data being output on a different flow to the accumulated debug data.

14. A method as claimed in claim 8, wherein the debug unit receives the throttle level from the shared hub.

15. A method as claimed in claim 14, wherein the shared hub comprises a buffer for storing data transported over the interface, the method comprising at the shared hub determining the throttle level in dependence on the state of the buffer.

16. A method as claimed in claim 14, wherein the shared hub received the throttle level from a device external to the integrated circuit chip.

17. A method as claimed in claim 8, wherein the debug unit comprises a buffer for storing debug data, the method comprising at the debug unit receiving the throttle level from itself in dependence on the state of the buffer.

18. An integrated circuit chip comprising:

a shared hub;

a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit;

between each respective debug unit and the shared hub an interface configured to;

transport data messages over each of a plurality of flows to which priorities are assignable;

transport control data for controlling the state of a debug unit on a flow having a first priority; and

transport debug data output by a debug unit as a result of debugging the peripheral circuit connected to that debug unit on a flow having a second priority, wherein the first priority is higher than the second priority.

19. An integrated circuit chip as claimed in claim 18, wherein the shared hub comprises a buffer configured to store data from a flow having a higher priority than another flow in preference to data from that other flow.

20. An integrated circuit chip as claimed in claim 18, wherein the shared hub comprises a physical buffer comprising a plurality of logical buffers, the shared hub being configured to store data from different flows in different logical buffers.